ADS7279 Datasheet, PDF (35/46 Pages) Texas Instruments – LOW-POWER, 14-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE

ADS7279
ADS7280
www.ti.com........................................................................................................................................................................................................ SBAS436 – MAY 2008
Figure 64 shows a slightly different scenario where CONVST is not shared by the second converter. Converters
#1 and #3 have the same CONVST signal. In this case, converter #2 simply passes the previous conversion data
downstream.
Cascaded Manual Trigger/Read While Sampling
(Use internal CCLK, EOC, and INT programmed as active low)
CS held low during the N times 16 bits transfer cycle
CONVST #1
CONVST #3
CONVST #2 = 1
EOC #1
(active low)
INT
(active low)
FS/CS #1
Common SCLK
SDO #1
FS/CS #2
FS/CS #3
SDO #2
SDO #3
SDI
Nth
t_CONV = 18 CCLKs
t_SAMPLE1 = 3 CCLKs Min
1……………………16 1……………………16 1……………………16
Nth from #1
N - 1th #2
Nth from #1
Nth from #3
N - 1th #2
Nth from #1
1101b
READ Result
1101b
READ Result
1101b
READ Result
Figure 64. Simplified Cascade Timing (Separate CONVST)
t₄
t₄
The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG
bit, chain mode, and the way a channel is selected (that is, auto channel select). These possible configurations
are listed in Table 6.
Table 6. Required SCLKs For Different Read-Out Mode Combinations
CHAIN MODE AUTO CHANNEL
ENABLED CFR.D5 SELECT CFR.D11 TAG ENABLED CFR.D1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
NUMBER OF SCLK
PER SPI READ
14
≥ 17
14
≥ 17
16
24
16
24
TRAILING BITS
None
MSB is TAG bit plus zero(s)
None
TAG bit plus seven zeros
None
TAG bit plus seven zeros
None
TAG bit plus seven zeros
Copyright © 2008, Texas Instruments Incorporated
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