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TSB41BA3 Datasheet, PDF (34/63 Pages) Texas Instruments – IEEE1394B THREE PORT CABLE TRANSCEIVER/ARBITER
TSB41BA3
IEEE 1394b THREEĆPORT CABLE TRANSCEIVER/ARBITER
SLLS155A − MAY 2003 − REVISED OCTOBER 2003
PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)
There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data
transmit, and data receive. The LLC issues a service request to read or write a PHY register, to request the PHY
to gain control of the serial-bus in order to transmit a packet, or to control arbitration acceleration.
The PHY may initiate a status transfer either autonomously or in response to a register read request from the
LLC.
The PHY initiates a receive operation whenever a packet is received from the serial-bus.
The PHY initiates a transmit operation after winning control of the serial-bus following a bus-request by the LLC.
The transmit operation is initiated when the PHY grants control of the interface to the LLC.
Table 11 and Table 12 show the encoding of the CTL0−CTL1 bus.
CTL0
0
0
1
1
Table 11. CTL Encoding When PHY Has Control of the Bus
CTL1
0
1
0
1
NAME
Idle
Status
Receive
Grant
DESCRIPTION
No activity (this is the default mode)
Status information is being sent from the PHY to the LLC.
An incoming packet is being sent from the PHY to the LLC.
The LLC has been given control of the bus to send an outgoing packet.
CTL0
0
0
1
1
Table 12. CTL Encoding When LLC Has Control of the Bus
CTL1
0
1
NAME
Idle
Hold
0 Transmit
1 Reserved
DESCRIPTION
The LLC releases the bus (transmission has been completed)
The LLC is holding the bus while data is being prepared for transmission, or indicating that another packet is to
be transmitted (concatenated) without arbitrating
An outgoing packet is being sent from the LLC to the PHY
None
LLC service request
To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC sends
a serial bit stream on the LREQ terminal as shown in Figure 13.
LR0
LR1
LR2
LR3
LR (n-2) LR (n-1)
Each cell represents one clock sample time, and n is the number of bits in the request stream.
Figure 13. LREQ Request Stream
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