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TPS54040 Datasheet, PDF (34/47 Pages) Texas Instruments – 0.5A, 42V STEP DOWN SWIFT™ DC/DC CONVERTER WITH ECO-MODE™
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TPS54040
SLVS918 – MARCH 2009................................................................................................................................................................................................... www.ti.com
Under Voltage Lock Out Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54040. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 8.9V (enabled). After the regulator starts switching, it should
continue to do so until the input voltage falls below 7.9V (UVLO stop).
The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN
pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example
application, a 332kΩ between Vin and EN and a 56.2kΩ between EN and ground are required to produce the 8.9
and 7.9 volt start and stop voltages.
Output Voltage and Feedback Resistors Selection
For the example design, 10.0 kΩ was selected for R2. Using Equation 1, R1 is calculated as 52.5 kΩ. The
nearest standard 1% resistor is 52.3 kΩ. Due to current leakage of the VSENSE pin, the current flowing through
the feedback network should be greater than 1 µA in order to maintain the output voltage accuracy. This
requirement makes the maximum value of R2 equal to 800 kΩ. Choosing higher resistor values will decrease
quiescent current and improve efficiency at low output currents but may introduce noise immunity problems.
Compensation
There are several methods used to compensate DC/DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual cross over frequency will usually be lower than the cross over frequency
used in the calculations. This method assume the crossover frequency is between the modulator pole and the
esr zero and the esr zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more
accurate design.
To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 41 and
Equation 42. For Cout, use a derated value of 21.2 µf. Use equations Equation 43 and Equation 44, to estimate
a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is
753 Hz and fzmod is 1505 kHz. Equation 43 is the geometric mean of the modulator pole and the esr zero and
Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 33.7 kHz and
Equation 44 gives 16.2 kHz. Use the lower value of Equation 43 or Equation 44 for an initial crossover frequency.
For this example, fco is 16.2 kHz. Next, the compensation components are calculated. A resistor in series with a
capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the
compensating pole.
¦p mod =
Ioutmax
2 × p × Vout × Cout
(41)
1
¦z mod =
2 ´ p ´ Resr × Cout
(42)
fco = f pmod´ fzmod
(43)
fco =
f pmod´
fsw
2
(44)
To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance,
gmps, is 1.9A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are
3.3V, 0.8V and 92µA/V, respectively. R4 is calculated to be 77.1 kΩ, use the nearest standard value of 76.8kΩ.
Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 2754 pF for
compensating capacitor C5, a 2700 pF is used on the board.
34
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