TAS2552_15 Datasheet, PDF (34/60 Pages) Texas Instruments – TAS2552 4.0-W Class-D Mono Audio Amplifier with Class-G Boost and Speaker Sense

TAS2552
SLAS898B – JANUARY 2014 – REVISED APRIL 2015
7.5.7 Register 0x05: Serial Interface Control Register 1
BIT NAME
7 WCLKDIR
6 BCLKDIR
5-4 CLKSPERFRAME
3-2 DATAFORMAT
1-0 WORDLENGTH
READ/WRITE
R/W
R/W
R/W
R/W
R/W
DEFAULT
0
0
00
00
00
DESCRIPTION
WCLK Direction
0 = WCLK is an input terminal
1 = WCLK is an output terminal
BCLK Direction
0 = BCLK is an input terminal
1 = BCLK is an output terminal
Clocks per Frame
00 = 32 clocks
01 = 64 clocks
10 = 128 clocks
11 = 256 clocks
Data Format
00 = I2S format
01 = DSP (PCM format)
10 = Right justified format (RJF)
11 = Left justified format (LJF)
Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
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7.5.8 Register 0x06: Serial Interface Control Register 2
This register sets the clock cycle offset between the WCLK edge to the MSB of serial interface patterns. This is
useful for TDM mode where multiple devices share DIN or DOUT lines.
BIT NAME
7-0 I2S_SHIFT_REG
READ /
WRITE
R/W
DEFAULT DESCRIPTION
0000 0000
Offset from WCLK to MSB in serial interface patterns.
0000 0000 = 0 bit offset
0000 0001 = 1 bit offset
….
1111 1111 = 255 bit offset
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