TLE2662 Datasheet, PDF (33/40 Pages) Texas Instruments – DUAL uPOWER JFET-INPUT OPERATIONAL AMPLIFIER WITH SWITCHED-CAPACITOR VOLTAGE CONVERTER

TLE2662
DUAL µPOWER JFET-INPUT OPERATIONAL AMPLIFIER
WITH SWITCHED-CAPACITOR VOLTAGE CONVERTER
SLOS118B – DECEMBER 1992 – REVISED AUGUST 1994
APPLICATION INFORMATION
pin functions (continued)
CAP+ is the positive side of input capacitor (CIN) and is alternately driven between V_CC and ground. When
driven to V_CC, CAP+ sources current from V_CC. When driven to ground, CAP+ sinks current to ground. CAP –
is the negative side of the input capacitor and is driven alternately between ground and SCOUT. When driven
to ground, CAP– sinks current to ground. When driven to SCOUT, CAP– sources current from COUT. In all
cases, current flow in the switches is unidirectional as should be expected when using bipolar switches.
OSC can be used to raise or lower the oscillator frequency or to synchronize the device to an external clock.
Internally, OSC is connected to the oscillator timing capacitor (C_t ≈ 150 pF), which is alternately charged and
discharged by current sources of ±7 µA, so that the duty cycle is approximately 50%. The TLE2662
switched-capacitor section oscillator is designed to run in the frequency band where switching losses are
minimized. However, the frequency can be raised, lowered, or synchronized to an external system clock if
necessary.
The frequency can be increased by adding an external capacitor (C2 in Figure 62) in the range of 5 pF – 20 pF
from CAP+ to OSC. This capacitor couples a charge into C_t at the switch transitions. This shortens the charge
and discharge time and raises the oscillator frequency. Synchronization can be accomplished by adding an
external pullup resistor from OSC to SCREF . A 20-kΩ pullup resistor is recommended. An open-collector gate
or an npn transistor can then be used to drive OSC at the external clock frequency as shown in Figure 62. The
frequency can be lowered by adding an external capacitor (C₁ in Figure 62) from OSC to ground. This increases
the charge and discharge times, which lowers the oscillator frequency.
1
1OUT
2
1IN –
3
1IN +
4
VCC _–
COUT
5
C1
SCOUT
+
6
SCREF
7
OSC
C2
SCIN
8
SCIN
16
VCC +
15
2OUT
14
2IN –
13
2IN +
12
CAP –
11
GND
10
CAP +
9
FB/SD
CIN
+
Figure 62. External Clock System
The feedback/shutdown (FB/SD) pin has two functions. Pulling FB/SD below the shutdown threshold ( ≈ 0.45 V)
puts the device into shutdown. In shutdown, the reference/regulator is turned off and switching stops. The
switches are set such that both CIN and COUT are discharged through the output load. Quiescent current in
shutdown drops to approximately 100 µA . Any open-collector gate can be used to put the TLE2662 into
shutdown. For normal (unregulated) operation, the device restarts when the external gate is shut off. In
TLE2662 circuits that use the regulation feature, the external resistor divider can provide enough pulldown to
keep the device in shutdown until the output capacitor (COUT) has fully discharged. For most applications
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