TAS5028 Datasheet, PDF (33/84 Pages) Texas Instruments – 8 Channel Digital Audio PWM Processor

TAS5028 Controls and Status
2 TAS5028 Controls and Status
The TAS5028 provides control and status information from both the I²C registers and device pins.
This section describes some of these controls and status functions. The I²C summary and detailed register
descriptions are contained in sections at the end of this document.
2.1 I²C Status Registers
The TAS5028 has two status registers that provide general device information. These are the General Status
Register 0 (0x01) and the Error Status Register (0x02).
2.1.1 General Status Register (0x01)
• Device identification code
• Clip indicator – The TAS5028 has a clipping indicator. Writing to the register clears the indicator.
• Bank switching is busy
2.1.2 Error Status Register (0x02)
• No internal errors (the valid signal is high)
• A clock error has occurred – These are sticky bits that are cleared by writing to the register.
- LRCLK error – When the number of MCLKs per LRCLK is incorrect
- SCLK error – When the number of SCLKS per LRCLK is incorrect
- Frame slip – When the number of MCLKs per LRCLK changes by more than 10 MCLK cycles
- PLL phase-lock error
• This error status register is normally used for system development only.
2.2 TAS5028 Pin Controls
The TAS5028 provide a number of terminal controls to manage the device operation. These controls are:
• RESET
• PDN
• BKND_ERR
• HP_SEL
• MUTE
2.2.1 Reset (RESET)
The TAS5028 is placed in the reset mode by setting the RESET terminal low or by the power up reset circuitry
when power is applied.
RESET is an asynchronous control signal that restores the TAS5028 to the hard mute state (M). Master
volume is immediately set to full attenuation (there is no ramp down). Reset initiates the device reset without
an MCLK input. As long as the RESET terminal is held low, the device is in the reset state. During reset, all
I²C and serial data bus operations are ignored.
Table 2 - 1 shows the device output signals while RESET is active.
Table 2 - 1. Device Outputs During Reset
SIGNAL
SIGNAL STATE
Valid
Low
PWM P-outputs
Low (M-State)
PWM M-outputs
Low (M-State)
SDA
Signal Input (not driven)
SLES112 — June 2004
TAS5028
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