TVP5147PFP_07 Datasheet, PDF (32/100 Pages) Texas Instruments – NTSC/PAL/SECAM 2x10-Bit Digital Video Decoder With Macrovision™ Detection,YPbPr Inputs,and 5-Line Comb Filter

Functional Description
Because SDA and SCL are kept open-drain at a logic-high output level or when the bus is not driven, the user
must connect SDA and SCL to a positive supply voltage via a pullup resistor on the board. The slave addresses
select signal, terminal 37 (I2CA), enables the use of two TVP5147 devices tied to the same I²C bus, because
it controls the least significant bit of the I²C device address.
Table 2−4. I²C Host Interface Terminal Description
SIGNAL
I2CA
SCL
SDA
TYPE
I
I
I/O
DESCRIPTION
Slave address selection
Input clock line
Input/output data line
2.6.1 Reset and I²C Bus Address Selection
The TVP5147 decoder can respond to two possible chip addresses. The address selection is made at reset
by an externally supplied level on the I2CA terminal. The TVP5147 decoder samples the level of terminal 37
at power up or at the trailing edge of RESETB and configures the I²C bus address bit A0. The I2CA terminal
has an internal pulldown resistor to pull the terminal low to set a zero.
Table 2−5. I²C Address Selection
A6
A5
A4
A3
A2
A1
A0 (I2CA)
R/W
1
0
1
1
1
0
0 (default)
1/0
1
0
1
1
1
0
1†
1/0
† _{If terminal 37 is strapped to DVDD via a 2.2-kΩ resistor, I2C device address A0 is set to 1.}
2.6.2 I²C Operation
HEX
B9/B8
BB/BA
Data transfers occur using the following illustrated formats.
S
10111000
ACK
Subaddress
ACK
Send data
ACK
P
Read from I²C control registers
S 10111000 ACK Subaddress ACK S 10111001 ACK Receive data NAK P
S = I²C bus start condition
P = I²C bus stop condition
ACK = Acknowledge generated by the slave
NAK = Acknowledge generated by the master, for multiple-byte read master with ACK each byte except
last byte
Subaddress = Subaddress byte
Data = Data byte. If more than one byte of data is transmitted (read and write), the subaddress pointer is
automatically incremented.
I²C bus address = Example shown that I²CA is in default mode. Write (B8h), read (B9h)
2.6.3 VBUS Access
The TVP5147 decoder has additional internal registers accessible through an indirect access to an internal
24-bit address wide VBUS. Figure 2−23 shows the VBUS register access.
24 TVP5147PFP
SLES099C—March 2007