TLV320AIC3106-Q1_15 Datasheet, PDF (32/103 Pages) Texas Instruments – LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY

TLV320AIC3106-Q1
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
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power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the
gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled
by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part
after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When the ADC
power-down flag is no longer set, the audio master clock can be shut down.
STEREO AUDIO ADC HIGH-PASS FILTER
Often in audio applications it is desirable to remove the dc offset from the converted audio data stream. The
TLV320AIC3106 has a programmable first-order high-pass filter which can be used for this purpose. The digital
filter coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients, N0,
N1, and D1. The transfer function of the digital high-pass filter is of the form:
H(z)
+
N0 ) N1
32768 * D1
z ^*1
z ^*1
(1)
Programming the left channel is done by writing to page 1, registers 65–70, and the right channel is programmed
by writing to page 1, registers 71–76. After the coefficients have been loaded, these ADC high-pass filter
coefficients can be selected by writing to page 0, register 107, bits D7–D6, and the high-pass filter can be
enabled by writing to page 0, register 12, bits D7–D4.
DIGITAL AUDIO PROCESSING FOR RECORD PATH
In applications where record only is selected, and DAC is powered down, the playback path signal processing
blocks can be used in the ADC record path. These filtering blocks can support high pass, low pass, band pass or
notch filtering. In this mode, the record only path has switches SW-D1 through SW-D4 closed, and reroutes the
ADC output data through the digital signal processing blocks. Since the DAC's Digital Signal Processing blocks
are being re-used, naturally the addresses of these digital filter coefficients are the same as for the DAC digital
processing and are located on Page 1, Registers 1-52. This record only mode is enabled by powering down both
DACs by writing to Page 0, Register 37, bits D7-D6 (D7=D6="0"). Next, enable the digital filter pathway for the
ADC by writing a "1" to Page 0, Register 107, bit D3. (Note, this pathway is only enabled if both DACs are
powered down.) This record only path can be seen in Figure 27.
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