SN54LVT8980 Datasheet, PDF (32/34 Pages) Texas Instruments – EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997
silicon errata
The descriptions and specifications included in this data sheet represent the intended performance of the
’LVT8990 device. In most cases, these descriptions and specifications also represent the actual performance
of silicon of a given revision. Specific exceptions are noted here.
item 1 – operation of host interface (STRB) asynchronous to CLKIN
The host interface, which is timed by STRB, is intended to be, and properly should be, fully asynchronous
relative to CLKIN. In short, the device should function as described in this data sheet regardless of the timing
relationship between applied STRB and CLKIN.
The ’LVT8990 “X” die, however, fails to function properly when STRB is not synchronous to CLKIN. Specifically,
STRB must be applied considering adequate setup time requirements as follows:
tsu
STRB high before CLKIN↑
SN74LVT8980
VCC = 3.3
± 0.3 V
VCC = 2.7 V
MIN MAX MIN MAX
25
25
UNIT
ns
A fix is proposed for device revision ’LVT8980A.
workaround
For an ’LVT8980 “X” die design, always operate the host interface (specifically, STRB) synchronously to CLKIN,
maintaining setup time requirements as given above. In most applications, this would mean that the eTBDC
CLKIN is driven from the same original clock source as the host CPU.
item 1 – read of TDI buffer while it is empty (not ready)
When a read is made to TDI buffer while it is empty (not ready), the RDY pin signal is specified to go low,
indicating that the eTBC is not presently ready to service the requested access. If, while STRB is held low,
subsequent processing of a scan command fills a byte in the TDI buffer, the RDY pin signal is specified to return
high, indicating that the eTBC is ready to complete the access. Correspondingly, the available byte of data from
TDI buffer should be latched onto the data bus such that the host can access this data.
The ’LVT8990 “X” die, however, does not function properly with respect to the actual data latched to the data
bus. That is, if a read is made to TDI buffer while it is empty (not ready), the RDY pin signal goes low as specified;
as well, if the STRB pin signal is held low, and further processing of a scan command fills a byte in the TDI buffer,
the RDY pin signal returns high as specified. However, at the same time that RDY returns high, the TDI data
byte should be latched onto the data bus. If this does not occur, the data that does appear on the data bus is
not valid.
A fix is proposed for device revision ’LVT8980A.
workaround
For an LVT8990 “X” design, always poll the TDI buffer (read status register, bit 7, TDIS) to ensure that it is ready
prior to a desired read to TDI buffer. Of course, such a software-polled mode versus the hardware-inserted
wait-states (RDY) mode (as originally specified, and as proposed to be fixed in ’LVT8980A device revision)
places more overhead on the CPU and likely reduces throughput as well.
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