PCI1451 Datasheet, PDF (32/141 Pages) Texas Instruments – PC Card Controller

Table 2–17. CardBus PC Card Interface Control (slots A and B)
TERMINAL
NAME
NO.
I/O
SLOT SLOT
A† B‡
FUNCTION
CAUDIO
L6 F10
I
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI4450
supports the binary audio mode and outputs a binary signal from the card to SPKROUT.
CBLOCK C2 D16 I/O CardBus lock. CBLOCK is used to gain exclusive access to a target.
CCD1
CCD2
F8 J19
L4 D10
I ^{CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and}
CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type.
CardBus device select. The PCI4450 asserts CDEVSEL to claim a CardBus cycle as the target device.
CDEVSEL E5 A18 I/O As a CardBus initiator on the bus, the PCI4450 monitors CDEVSEL until a target responds. If no target
responds before time-out occurs, then the PCI4450 terminates the cycle with an initiator abort.
CFRAME
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted
F2 D15 I/O to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When CFRAME is deasserted, the CardBus bus transaction is in the final data phase.
CGNT
E4 B18
I
CardBus bus grant. CGNT is driven by the PCI4450 to grant a CardBus PC Card access to the CardBus
bus after the current data transaction has been completed.
CINT
K2 E11
I
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the
host.
CIRDY
CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data
F4 B16 I/O phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and
CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.
CPERR
D1
C18
I/O
CardBus parity error. CPERR reports parity errors during CardBus transactions, except during special
cycles. It is driven low by a target two clocks following that data when a parity error is detected.
CREQ
J4 A13
I ^{CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus}
bus as an initiator.
CSERR
K4 F11
CardBus system error. CSERR reports address parity errors and other system errors that could lead
I ^{to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak}
pullup, and may take several CCLK periods. The PCI4450 can report CSERR to the system by
assertion of SERR on the PCI interface.
CSTOP
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus
D2 B19 I/O transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that
do not support burst data transfers.
CSTSCHG L1 A10
CardBus status change. CSTSCHG alerts the system to a change in the card’s status and is used as
I _{a wake-up mechanism.}
CTRDY
CardBus target ready. CTRDY indicates the CardBus target’s ability to complete the current data phase
F5 B17 I/O of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY
are asserted; until this time, wait states are inserted.
CVS1
CVS2
K1 B11
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with
I/O CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and
H6 A14
card type.
† _{Terminal name for slot A is preceded with A_. For example, the full name for terminal M1 is A_CAUDIO.}
‡ _{Terminal name for slot B is preceded with B_. For example, the full name for terminal C11 is B_CAUDIO.}
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