ADS5481_0811 Datasheet, PDF (32/42 Pages) Texas Instruments – 16-Bit, 80/105/135-MSPS Analog-to-Digital Converters

ADS5481
ADS5482
ADS5483
SLAS565A – JUNE 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com
100
90
80
10 MHz
30 MHz
70 MHz
70
100 MHz
60
231 MHz
50
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Clock Common Mode Voltage − V
G062
Figure 72. SFDR versus Clock Common Mode
100
10 MHz
90
70 MHz
80 30 MHz
81
79
77
75
70 MHz
73
10 MHz
100 MHz
71
30 MHz
69
67
231 MHz
65
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Clock Common Mode Voltage − V
G063
Figure 73. SNR versus Clock Common Mode
f_S = 135 MSPS
A_IN = −1 dBFS
Clock Input = 3 Vpp
70
60
50
0
231 MHz
100 MHz
10 20 30 40 50 60 70 80 90
Clock Duty Cycle − %
Figure 74. SFDR vs Clock Duty Cycle
100
G064
The ADS5483 is capable of achieving 78.2 dBFS SNR at 100 MHz of analog input frequency. In order to achieve
the SNR at 100 MHz the clock source rms jitter (at the ADC clock input pins) must be at most 205 fsec in order
for the total rms jitter to be 220 fsec due to internal ADC aperture jitter of ~80 fsec. A summary of maximum
recommended rms clock jitter as a function of analog input frequency for the ADS5483 is provided in Table 2.
The equations used to create the table are presented and can be used to estimate required clock jitter for
virtually any pipeline ADC.
Table 2. Recommended Approximate RMS Clock Jitter for ADS5483
ANALOG INPUT FREQUENCY
(MHz)
1
10
70
100
130
170
230
300
MEASURED SNR
(dBc)
78.2
78
77.8
77.2
76
75.8
75.1
73.2
TOTAL JITTER
(fsec rms)
19581
2004
300
220
177
152
122
116
MAXIMUM CLOCK JITTER
(fsec rms)
19581
2002
289
205
158
129
92
84
32
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