TMS470R1A64 Datasheet, PDF (31/46 Pages) Texas Instruments – 16/32-Bit RISC Flash Microcontroller

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SPIn MASTER MODE TIMING PARAMETERS
TMS470R1A64
16/32-Bit RISC Flash Microcontroller
SPNS099 – NOVEMBER 2004
SPIn MASTER MODE EXTERNAL TIMING PARAMETERS
(CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)^(1)(2)(3) (see Figure 12)
NO.
MIN
MAX
UNIT
1
t_c(SPC)M
Cycle time, SPInCLK⁽⁴⁾
100
256t_c(ICLK)
ns
2 ⁽⁵⁾
t_w(SPCH)M
t_w(SPCL)M
Pulse duration, SPInCLK high (clock polarity = 0)
Pulse duration, SPInCLK low (clock polarity = 1)
0.5t_c(SPC)M - t_r 0.5t_c(SPC)M + 5 _ns
0.5t_c(SPC)M - t_f 0.5t_c(SPC)M + 5
3 ⁽⁵⁾
t_w(SPCL)M
t_w(SPCH)M
Pulse duration, SPInCLK low (clock polarity = 0)
Pulse duration, SPInCLK high (clock polarity = 1)
0.5t_c(SPC)M - t_f 0.5t_c(SPC)M + 5 _ns
0.5t_c(SPC)M - t_r 0.5t_c(SPC)M + 5
4 ⁽⁵⁾
t_{d(SPCH-SIMO)M} Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0)
0
t_{d(SPCL-SIMO)M} Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1)
0
10
ns
10
t_{v(SPCL-SIMO)M}
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 0)
t_c(SPC)M - 5 - t_f
5 ⁽⁵⁾
ns
t_{v(SPCH-SIMO)M}
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
t_c(SPC)M - 5 - t_r
t_{su(SOMI-SPCL)M}
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 0)
6 ⁽⁵⁾
t_{su(SOMI-SPCH)M}
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 1)
6
ns
6
t_{v(SPCL-SOMI)M}
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 0)
4
7 ⁽⁵⁾
ns
t_{v(SPCH-SOMI)M}
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 1)
4
(1) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
(2) t_c(ICLK) = interface clock cycle time = 1/f_(ICLK)
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(4) When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_c(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0: t_c(SPC)M = 2t_c(ICLK)≥ 100 ns.
(5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
SPInSOMI
6
7
Master In Data
Must Be Valid
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 0)
31