TMS320VC5506 Datasheet, PDF (31/120 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
3.1.4 Memory Maps
3.1.4.1 PGE Package Memory Map
The PGE package features 14 address bits representing 32K-/16K-byte linear address for asynchronous
memories per CE space. Due to address row/column multiplexing, address reach for SDRAM devices is
4M bytes for each CE space. The largest SDRAM device that can be used with the 5506 in a PGE package
is 128M-bit SDRAM.
Byte Address
(Hex)^†
000000
0000C0
008000
010000
Memory Blocks
MMR (Reserved)
DARAM
DARAM^‡
SARAM^§
Block Size
(32K − 192) Bytes
32K Bytes
64K Bytes
020000
040000
400000
800000
C00000
FF0000
Reserved
External^¶ − CE0
External^¶ − CE1
External^¶ − CE2
External^¶ − CE3
32K/16K Bytes − Asynchronousk
4M Bytes − 128K Bytes SDRAM^#
32K/16K Bytes − Asynchronousk
4M Bytes − SDRAM
32K/16K Bytes − Asynchronousk
4M Bytes − SDRAM
32K/16K Bytes − Asynchronousk
4M Bytes − SDRAM (MPNMC = 1)
4M Bytes − 64K Bytes if internal ROM selected (MPNMC = 0)
ROM^||
External^¶ − CE3
(if MPNMC=0) (if MPNMC=1)
64K Bytes
FFFFFF
† _{Address shown represents the first byte address in each block.}
‡ _{Dual-access RAM (DARAM): two accesses per cycle per block, 8 blocks of 8K bytes.}
§ _{Single-access RAM (SARAM): one access per cycle per block, 8 blocks of 8K bytes.}
¶ _{External memory spaces are selected by the chip-enable signal shown (CE[0:3]). Supported memory types include: asynchronous static}
RAM (SRAM) and synchronous DRAM (SDRAM).
# _{The minus 128K bytes consists of 32K-byte DARAM access, 32K-byte DARAM, and 64K-byte SARAM.}
|| _{Read-only memory (ROM): one access every two cycles.}
k32K bytes for 16-bit-wide memory. 16K bytes for 8-bit-wide memory.
Figure 3−2. TMS320VC5506 Memory Map (PGE Package)
October 2006 − Revised January 2008
SPRS375C
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