TMS320VC5421 Datasheet, PDF (31/88 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
direct memory access (DMA) controller (continued)
Hex
Data†
00 0000
Reserved
00 001F
00 0020
McBSP
DXR/DRR
00 005F ^{MMRegs Only}
00 0060
On-Chip
DARAM A/B
(32K Words)
Prog/Data
Hex ^{Program Page 0‡}
00 0000
Reserved
00 001F
00 0020 ^McBSP
DXR/DRR
00 005F ^{MMRegs Only}
00 0060
On-Chip
DARAM A
(32K Words)
Prog/Data
Hex ^{Program Page 1‡ Hex Program Page 2‡} Hex ^{Program Page 3‡}
01 0000
02 0000
Reserved
02 001F
03 0000
02 0020 _McBSP
DXR/DRR
On-Chip
Shared
DARAM 0
(32K Words)
Program
Only
02 005F ^{MMRegs Only}
02 0060
On-Chip
DARAM B
(32K Words)
Prog/Data
On-Chip
Shared
DARAM 2
(32K Words)
Program
Only
00 7FFF
00 8000
Subsystem A
00 7FFF
00 8000
01 7FFF
01 8000
Shared 0
02 7FFF ^{Subsystem B} 03 7FFF ^{Shared 2}
02 8000
03 8000
On-Chip
SARAM A/B
(32K Words)
Data Only
On-Chip
SARAM A
(32K Words)
Data Only
On-Chip
Shared
DARAM 1
(32K Words)
Program
Only
On-Chip
SARAM B
(32K Words)
Data Only
On-Chip
Shared
DARAM 3
(32K Words)
Program
Only
00 FFFF
Subsystem A
00 FFFF
01 FFFF
Shared 1
Subsystem B
02 FFFF
03 FFFF ^{Shared 3}
† _{DMD/DMS = 01}
‡ _{DMD/DMS = 00}
NOTES: A. All local memory is available to the DMA.
B. All I/O memory accesses by the DMA (DMD/DMS = 10) are mapped to the core-to-core FIFO.
C. In pages 00 and 02, in the range of 0020–005F, only the following memory mapped registers are accessible: 20,21,30,31,40,41
(read only), 22,23,32,33,42,43 (write only).
Figure 13. On-Chip Memory Map Relative to DMA (DLAXS/SLAXS = 0)
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