DAC5687_15 Datasheet, PDF (31/80 Pages) Texas Instruments – 16-BIT, 500 MSPS 2´–8´ INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)

DAC5687
www.ti.com
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
Register Name: DAC_CLK_CNTL—Address: 0x1A, Default = 0x00
BIT 7
BIT 0
Factory use only
0
0
0
0
0
0
0
0
Reserved for factory use only.
Register Name: ATEST—Address: 0x1B, Default = 0x00
BIT 7
BIT 0
atest(4:0)
phstr_del(1:0)
unused
0
0
0
0
0
0
0
0
atest(4:0): Can be used to enable clock output at the PLLLOCK pin according to Table 5. Pin EXTLO must be
open when atest(4:0) is not equal to 00000.
Table 5. PLLLOCK Output
atest(4:0)
PLLLOCK Output Signal
PLL Enabled (PLLVDD = 3.3 V)
PLL Disabled (PLLVDD = 0 V)
11101
11110
11111
All others
f_DAC
f_DAC divided by 2
f_DAC divided by 4
Normal operation
Normal operation
Normal operation
Normal operation
phstr_del: Adjusts the initial phase of the f_S/2 and f_S/4 blocks cmix block after PHSTR.
Register Name: DAC_TEST—Address: 0x1C, Default = 0x00
BIT 7
BIT 0
Factory use only
phstr_clkdiv_sel
0
0
0
0
0
0
0
0
phstr_clkdiv_sel: Selects the clock used to latch the PHSTR input when restarting the internal dividers. When
set, the full DAC sample rate CLK2 signal latches PHSTR, and when cleared, the divided down input clock
signal latches PHSTR.
Address: 0x1D, 0x1E, and 0x1F – Reserved
Writes have no effect and reads are 0x00.
Copyright © 2005–2006, Texas Instruments Incorporated
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