TPS51650_15 Datasheet, PDF (30/51 Pages) Texas Instruments – Dual-Channel (3-Phase CPU/2-Phase GPU) SVID, D-CAP+™ Step-Down Controller for IMVP-7 VCORE with Two Integrated Drivers

TPS51650, TPS59650
SLUSAV7 – JANUARY 2012
www.ti.com
AutoBalance™ Current Sharing
The basic mechanism for current sharing is to sense the average phase current, then adjust the pulse width of
each phase to equalize the current in each phase. (See Figure 50.)
The PWM comparator (not shown) starts a pulse when the feedback voltage meets the reference. The VBAT
voltage charges C_t(ON) through R_t(ON). The pulse is terminated when the voltage at C_t(ON) matches the t_(ON)
reference, normally the DAC voltage (V_DAC).
The circuit operates in the following fashion, using Figure 50 as the block diagram. First assume that the 5-µs
averaged value of I1 = I2 = I3. In this case, the PWM modulator terminates at V_DAC, and the normal pulse width
is delivered to the system. If instead, I1 > I_AVG, then an offset is subtracted from V_DAC, and the pulse width for
Phase 1 is shortened, reducing the current in Phase 1 to compensate. If I1 < I_AVG, then a longer pulse is
produced, again compensating on a pulse-by-pulse basis.
VBAT 37
CCSP1 4
CCSN1 5
+
Current
Amplifier
5 ms
Filter
V_DAC
K x (I1-I_AVG)
+
I_AVG
R_T(on)
+
C_T(on)
PWM1
R_T(on)
CCSP2 7
CCSN2 6
+
Current
Amplifier
5 ms
Filter
Averaging
Circuit
V_DAC
K x (I2-I_AVG)
+
I_AVG
I_AVG
+
C_T(on)
PWM2
R_T(on)
CCSP3 8
CCSN3 9
+
Current
Amplifier
5 ms
Filter
V_DAC
K x (I3-I_AVG)
+
I_AVG
+
C_T(on)
PWM3
Figure 50. Schematic Representation of AutoBalance Current Sharing
UDG-11036
Dynamic VID and Power-State Changes
In IMVP-7, there are 3 basic types of VID changes:
• SetVID-Fast
• SetVID-Slow
• SetVID-Decay
SetVID-Fast change and a SetVID-Slow change automatically puts the power state in PS0. A SetVID-Decay
change automatically puts the power state in PS2.
30
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