TPS40077_07 Datasheet, PDF (30/43 Pages) Texas Instruments – HIGH-EFFICIENCY, MIDRANGE-INPUT, SYNCHRONOUS BUCK CONTROLLER WITH VOLTAGE FEED-FORWARD

TPS40077
SLUS714 – JANUARY 2007
www.ti.com
Boost Voltage, CBOOST and DBOOST (Optional)
To be able to drive an N-channel MOSFET in the switch location of a buck converter, a capacitor charge pump
or boost circuit is required. The TPS40077 contains the elements for this boost circuit. The designer must only
add a capacitor, CBOOST, from the switch node of the buck power stage to the BOOST pin of the IC. Selection
of this capacitor is based on the total gate charge of the switching MOSFET and the allowable ripple on the
boost voltage, ∆V_BOOST. A ripple of 0.2 V is assumed for this design. Using these two parameters and
Equation 43, the minimum value for CBOOST can be calculated.
CBOOST
u
Q _g(TOTAL)
DV_BOOST
(43)
The total gate charge of the switching MOSFET is 23 nC. A minimum CBOOST of 0.092 µF is required. A 0.1
µF capacitor was chosen. This capacitor must be able to withstand the maximum input voltage plus the
maximum voltage on DBP. This is 13.2 V plus 9.0 V, which is 22.2 V. A 50-V capacitor is used.
To reduce losses in the TPS40077 and to increase the available gate voltage for the switching MOSFET, an
external diode can be added between the DBP pin and the BOOST pin of the IC. A small-signal Schottky diode
should be used here, such as the BAT54.
Closing the Feedback Loop, R_Z1, R_P1, R_PZ2, R_SET1, R_SET2, C_Z2, C_P2, and C_PZ1
A graphical method is used to select the compensation components. This is a standard feed-forward buck
converter. Its PWM gain is given by Equation 44.
K_PWM
^
V_UVLO
1V
(44)
The ramp voltage is 1 V at the UVLO voltage. Because of the feed-forward compensation, the programmed
UVLO voltage is the voltage that sets the PWM gain.
The gain of the output LC filter is given by Equation 45.
K_LC +
1)s
1 ) s ESR COUT
LOUT
ROUT
)
s²
LOUT
COUT
(45)
The PWM and LC gain is
G_c(s) + K_PWM
K_LC
V_UVLO
1V
1 ) s ESR COUT
1)s
LOUT
ROUT
)
s²
LOUT
COUT
(46)
To plot this on a Bode plot, the dc gain must be expressed in dB. The dc gain is equal to KPWM. To express
this in dB, take its logarithm and multiply by 20. For this converter, the dc gain is
ƪ ƫ DCGAIN + 20
log
V_UVLO
V_RAMP
+ 20
log(7) + 16.9 dB
(47)
Also, the pole and zero frequencies should be calculated. A double pole is associated with the LC and a zero is
associated with the ESR of the output capacitor. The frequencies where these occur can be calculated using
equations,
f_{LC_Pole} + _2p
1
Ǹ_LOUT
+ 4.3 kHz
COUT
(48)
f_{ESR_Zero} + _2p
1
ESR
COUT ^{+ 2.1 kHz}
(49)
These are shown in the Bode plot of Figure 31.
30
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