TLV320AIC3206_15 Datasheet, PDF (30/51 Pages) Texas Instruments – TLV320AIC3206 Ultra Low-Power Stereo Audio Codec

TLV320AIC3206
SLAS649C – DECEMBER 2010 – REVISED NOVEMBER 2014
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10.3.6 Digital Audio IO Interface
Audio data flows between the host processor and the TLV320AIC3206 on the digital audio data serial interface,
or audio bus. This very flexible bus includes left or right-justified data options, support for I²S or PCM protocols,
programmable data length options, a TDM mode for multichannel operation, very flexible master-slave
configurability for each bus clock line, and the ability to communicate with multiple devices within a system
directly.
The audio bus of the TLV320AIC3206 can be configured for left or right-justified, I²S, DSP, or TDM modes of
operation, where communication with standard PCM interfaces is supported within the TDM mode. These modes
are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Page 0, Register 27,
D(5:4). In addition, the word clock and bit clock can be independently configured in either Master or Slave mode,
for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a
frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock
corresponds to the maximum of the selected ADC and DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,
this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0,
Register 30. The number of bit-clock pulses in a frame may need adjustment to accommodate various word
lengths, and to support the case when multiple TLV320AIC3206s may share the same audio bus.
The TLV320AIC3206 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. Control the offset in terms of number of bit-clocks by programming Page 0, Register 28.
The TLV320AIC3206 also has the feature to invert the polarity of the bit-clock used to transfer the audio data as
compared to the default clock polarity used. This feature can be used independently of the mode of audio
interface chosen. Page 0, Register 29, D(3) configures bit clock polarity.
The TLV320AIC3206 further includes programmability (Page 0, Register 27, D(0)) to place the DOUT line into a
hi-Z (3-state) condition during all bit clocks when valid data is not being sent. By combining this capability with
the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be
accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data
bus is powered down while configured in master mode, the pins associated with the interface are put into a hi-Z
output condition.
By default when the word-clocks and bit-clocks are generated by the TLV320AIC3206, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This intermittent clock operation
reduces power consumption. However, it also supports a feature when both the word clocks and bit-clocks can
be active even when the codec in the device is powered down. This continuous clock feature is useful when
using the TDM mode with multiple codecs on the same bus, or when word-clock or bit-clocks are used in the
system as general-purpose clocks.
10.3.7 Clock Generation and PLL
The TLV320AIC3206 supports a wide range of options for generating clocks for the ADC and DAC sections as
well as interface and other control blocks. The clocks for ADC and DAC require a source reference clock. This
clock can be provided on variety of device pins such as MCLK, BCLK or GPI pins. The CODEC_CLKIN can then
be routed through highly-flexible clock dividers to generate the various clocks required for the ADC and DAC
sections. In the event that the desired audio clocks cannot be generated from the reference clocks on MCLK,
BCLK or GPIO, the TLV320AIC3206 also provides the option of using the on-chip PLL which supports a wide
range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN the
TLV320AIC3206 provides several programmable clock dividers to help achieve a variety of sampling rates for
ADC, DAC and clocks for the processing block.
To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of
the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required
internal clock signals at very low power consumption. For cases where such master clocks are not available, the
built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master
clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible
enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL
is used to generate some other clock that is only used outside the TLV320AIC3206.
For more detailed information see the TLV320AIC3206 Application Reference Guide, SLAA463.
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