SM320C6713-EP Datasheet, PDF (30/123 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SM320C6713-EP
SM320C6713B-EP
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SGUS049H – AUGUST 2003 – REVISED SEPTEMBER 2008
5 DEVICE CONFIGURATIONS
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On the C6713/13B devices, bootmode and certain device configurations/peripheral selections are
determined at device reset, while other device configurations/peripheral selections are
software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200]
after device reset.
5.1 Device Configurations at Device Reset
Table 5-1 describes the C6713 and C6713B device configuration pins, which are set up via internal or
external pullup/pulldown resistors through the HPI data pins (HD[4:3], HD8, HD12 [13B only]), and
CLKMODE0 pin. These configuration pins must be in the desired state until reset is released. For more
details on these device configuration pins, see the Terminal Functions table and the Debugging
Considerations section of this data sheet.
Table 5-1. Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12 [13B only], and CLKMODE0)⁽¹⁾
CONFIGURATION
PIN
HD12
HD8
HD[4:3]
(BOOTMODE)
CLKMODE0
GDP
FUNCTIONAL DESCRIPTION
C15
B17
C19, C20
C4
EMIF Big Endian mode correctness (EMIFBE) [C6713B only]
For a C6713BGDP:
0 – The EMIF data will always be presented on the ED[7:0] side of the bus, regardless of the
endianess mode (Little/Big Endian).
1 – In Little Endian mode (HD8 = 1), the 8-bit or 16-bit EMIF data will be present on the
ED[7:0] side of the bus.
In Big Endian mode (HD8 = 0), the 8-bit or 16-bit EMIF data will be present on the
ED[31:24] side of the bus [default].
For a C6713BPYP, when Big Endian mode is selected (LENDIAN = 0), for proper device operation the
EMIFBE pin must be externally pulled low.
This enhancement is not supported on the C6713 device.
For proper C6713 device operation, do not oppose the internal pullup (IPU) resistor on this pin.
This new functionality does not affect systems using the current default value of HD12 = 1. For more
detailed information on the big endian mode correctness, see the EMIF Big Endian Mode Correctness
[C6713B only] portion of this data sheet.
Device Endian mode (LEND)
0 – System operates in Big Endian mode
1 – System operates in Little Endian mode (default)
Bootmode Configuration pins (BOOTMODE)
00 – CE1 width 32-bit, HPI boot/emulation boot
01 – CE1 width 8-bit, asynchronous external ROM boot with default timings (default mode)
10 – CE1 width 16-bit, asynchronous external ROM boot with default timings
11 – CE1 width 32-bit, asynchronous external ROM boot with default timings
For more detailed information on these bootmode configurations, see the Bootmode section of this
data sheet.
Clock generator input clock source select
0 – Reserved. Do not use.
1 – CLKIN square wave [default]
This pin must be pulled to the correct level even after reset.
(1) All other HD pins [HD [15, 13:9, 7:5, 2:0] (for 13) or HD [15, 13, 11:9, 7:5, 2:0] (for 13B)] have pullups/pulldowns (IPUs or IPDs). For
proper device operation of the HD [15, 13:9, 7, 1, 0] (for 13) or HD [13, 11:9, 7, 1, 0] (for 13B), do not oppose these pins with external
pullups/pulldowns at reset; however, the HD[6, 5, 2] (for 13) or HD[15, 6, 5, 2] (for 13B) pins can be opposed and driven during reset.
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DEVICE CONFIGURATIONS
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