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| LM10500_15 Datasheet, PDF (30/40 Pages) Texas Instruments – 5A Step-Down Energy Management Unit (EMU) With PowerWise Adaptive Voltage Scaling (AVS) | |||
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LM10500
SNVS630G â SEPTEMBER 2009 â REVISED MARCH 2013
The compensation network transfer function is:
www.ti.com
(33)
With above equations, the loop gain
T = Gain0Fp(s)Fh(s)Fcomp(s)
(34)
can be plotted and more accurate loop performance metrics (crossover frequency and phase margin) can be
found.
HIGH-FREQUENCY CONSIDERATIONS
Fh(s) represents the additional magnitude and phase drop around fs/2 caused by the switching behavior of the
current mode converter. Fh(s) contains a pair of double poles with quality factor Qp at half of the switching
frequency. It is a good idea to check that Qp is between 0.15 and 2, ideally around 0.6. If Qp is too high, the
resonant peaking at fs/2 could become severe and coincide with subharmonic oscillations in the duty cycle and
inductor current. If Qp is too low, the two complex poles split, the converter begins to act like a voltage mode
controlled converter and the compensation scheme used above should be changed.
Fp(s) also contains the ESR zero of the output capacitors:
fESR
=
1
2SCOUTESR
(35)
In a typical ceramic capacitor design, fESR is at least three times higher than the desired crossover frequency fc. If
fESR is lower tha fs/2, an additional capacitor Cc2 can be added between the COMP pin and AGND to give a high-
frequency pole.
Cc2
=
1
2SRcfESR
(36)
CC2 should be and usually is much smaller than CC1 to avoid affecting the compensation zero.
BOOTSTRAP CAPACITOR
A ceramic capacitor is needed between the CBOOT pin to the SW node to supply the gate drive charge when
the high-side switch is turning ON. The capacitance should be large enough to supply the charge without
significant voltage drop. A 0.1 µF bootstrap capacitor is recommended in LM10500 applications.
POWERWISE INTERFACE ADDRESS SELECTION
External 1% resistor connecting between the ADDR pin to AGND sets the PWI address.
PWI Standard
RPWI1.0
RPWI2.0-0
RPWI2.0-1
RPWI2.0-2
RPWI2.0-3
Description
Address selection resistor for PWI-1.0
Address selection resistor for PWI-2.0, address 0
Address selection resistor for PWI-2.0, address 1
Address selection resistor for PWI-2.0, address 2
Address selection resistor for PWI-2.0, address 3
Typ
Unit
â¤20
kâ¦
40.2
kâ¦
60.4
kâ¦
80.6
kâ¦
100
kâ¦
The external resistance is only sensed one time when the part is powered up. If the address selection resistor is
modified after power up, it wonât take effect until a power cycling is performed.
VDD1 AND VDD2 BYPASS CAPACITORS
VDD1 and VDD2 pins are internal LDO outputs. As previously mentioned, the two LDOs are used for internal
circuits only and should not be substantially loaded.
Bypass capacitors are needed to stabilize the LDOs. Ceramic capacitors within a specified range should be used
to meet stability requirements. The dielectric should be X5R, X7R, or better and rated for the required operating
temperature range. Use the following table to choose suitable LDO bypass capacitor.
30
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Copyright © 2009â2013, Texas Instruments Incorporated
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