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BQ27510_08 Datasheet, PDF (30/36 Pages) Texas Instruments – System-Side Impedance Track™ Fuel Gauge With Direct Battery Connection
bq27510
SLUS816A – MARCH 2008 – REVISED JUNE 2008.......................................................................................................................................................... www.ti.com
COMMUNICATIONS
I2C INTERFACE
The 27510 supports the standard I2C read, incremental read, quick read, one byte write, and incremental write
functions. The 7 bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as
1010101. The 8-bit device address will therefore be 0xAA or 0xAB for write or read, respectively.
Host generated
bq27510 generated
S ADDR[6:0] 0 A CMD[7:0] A DATA [7:0] A P S ADDR[6:0] 1 A DATA [7:0] N P
(a) 1-byte write
(b) quick read
S ADDR[6:0] 0 A CMD[7:0] A Sr ADDR[6:0] 1 A DATA[7:0] N P
(c) 1- byte read
S ADDR[6:0] 0 A CMD[7:0] A Sr ADDR[6:0] 1 A DATA[7:0] A . . . DATA[7:0] N P
(d) incremental read
S ADDR[6:0] 0 A CMD[7:0] A DATA [7:0] A DATA [7:0]
(e) incremental write
(S = Start, Sr = Repeated Start, A = Acknowledge, N = No Acknowledge, and P = Stop).
Figure 4. Supported I2C Formats
A ... A P
The “quick read” returns data at the address indicated by the address pointer. The address pointer, a register
internal to the I2C communication engine, will increment whenever data is acknowledged by the bq27510 or the
I2C master. “Quick writes” function in the same manner and are a coS = Start, Sr = Repeated Start, A =
Achnowledge, nvenient means of sending multiple bytes to consecutive command locations (such as two-byte
commands that require two bytes of data)
The following command sequences are not supported:
Attempt to write a read-only address (NACK after data sent by master):
S ADDR[6:0] 0 A CMD[7:0]
A DATA[7:0]
AP
Attempt to read an address above 0x6B (NACK command):
S
ADDR[6:0]
0 A CMD[7:0] N P
The I2C engine will release both SDA and SCL if the I2C bus is held low for t(BUSERR). If the bq27510 was holding
the lines, releasing them will free the master to drive the lines. If an external condition is holding either of the
lines low, the I2C engine will enter the low power sleep mode.
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