UCC28C40 Datasheet, PDF (3/19 Pages) Texas Instruments – BICMOS LOW POWER CURRENT MODE PWM CONTROLLER

UCC28C40, UCC28C41, UCC28C42, UCC28C43, UCC28C44, UCC28C45
UCC38C40, UCC38C41, UCC38C42, UCC38C43, UCC38C44, UCC38C45
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
electrical characteristics V_DD = 15 V (See Note 1), R_T = 10 kΩ, C_T = 3.3 nF, C_VDD = 0.1µF and no load
on the outputs, T_A = −40°C to 105°C for the UCC28C4x and T_A = 0°C to 70°C for the UCC38C4x,
T_A = T_J (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
Reference Section
Output voltage, initial accuracy
Line regulation
Load regulation
TA = 25°C
IOUT = 1mA
VDD = 12 V to 18 V
1mA to 20mA
4.9
5.0
5.1
V
0.2
20 mV
3
25 mV
Temperature stability
See Note 2
0.2
0.4 mV/°C
Total output variation
See Note 2
4.82
5.18
V
Output noise voltage
Long term stability
Output short circuit
10 Hz to 10 kHz, TA = 25°C,
1000 hours,
TA = 125°C,
See Note 2
See Note 2
50
µV
5
25 mV
–30 –45 –55 mA
Oscillator Section
Initial accuracy
Voltage stability
Temperature stability
Amplitude
TA = 25°C,
See Note 3
VDD = 12 V to 18 V
TMIN to TMAX, See Note 2
RT/CT Pin peak-to-peak
50.5
53
55 kHz
0.2% 1.0%
1% 2.5%
1.9
V
Discharge current
TA = 25°C,
RT/CT = 2 V,
RT/CT = 2 V,
See Note 4
See Note 4
7.7
8.4
9.0 mA
7.2
8.4
9.5 mA
Error Amplifier Section
Feedback input voltage, initial accuracy
Feedback input voltage, total variation
Input bias current
Open-loop voltage gain (AVOL)
Unity gain bandwidth
VCOMP = 2.5 V, TA = 25°C
VCOMP = 2.5 V,
VFB = 5.0 V
VOUT = 2 V to 4 V
See Note 2
2.475
2.45
65
1.0
2.500
2.50
–0.1
90
1.5
2.525
2.55
–2.0
V
V
µA
dB
MHz
Power supply rejection ratio (PSRR)
Output sink current
Output source current
High-level output voltage (VOH)
Low-level output voltage (VOL)
Current Sense Section
VDD = 12 V to 18 V
VFB = 2.7 V,
VCOMP = 1.1 V
VFB = 2.3 V,
VCOMP = 5V
VFB = 2.7 V,
RLOAD = 15 k to GND
VFB = 2.7 V,
RLOAD = 15 k to VREF
60
2
14
–0.5 –1.0
5
6.8
0.1
dB
mA
mA
V
1.1
V
Gain
See Note 5, 6
2.85 3.00 3.15 V/V
Maximum input signal
Power supply rejection ratio (PSRR)
VFB < 2.4 V
VDD = 12 V to 18 V, See Note 2, 5
0.9
1.0
1.1
V
70
dB
Input bias current
–0.1 –2.0 µA
CS to output delay
35
70 ns
COMP to CS offset
VCS = 0 V
1.15
V
NOTE: 1. Adjust VDD above the start threshold before setting at 15 V.
NOTE: 2. Ensured by design. Not production tested.
NOTE: 3. Output frequencies of the UCC38C41, UCC38C44 and the UCC38C45 are half the oscillator frequency.
NOTE: 4. Oscillator discharge current is measured with RT = 10 kΩ to VREF.
NOTE: 5. Parameter measured at trip point of latch with VFB = 0 V.
NOTE:
6.
Gain
is
defined
as
ACS
+
DVCOM
DVCS
,
0V
¬
VCS
¬
900mV
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