TSL218 Datasheet, PDF (3/8 Pages) Texas Instruments – 512 × 1 PIXEL LINEAR ARRAY

TSL218
512 × 1 PIXEL LINEAR ARRAY
SOES014B – AUGUST 1994 – REVISED NOVEMBER 1995
sense node
On completion of the integration period, the charge contained in each pixel is transferred in turn to the sense
node under the control of the CLK and SI signals. The signal voltage generated at this node is directly
proportional to the amount of charge and inversely proportional to the capacitance of the sense node.
reset
An internal reset signal is generated by the nonoverlapping clock generator (NOCG) and occurs every clock
cycle. Reset establishes a known voltage on the sense node in preparation for the next charge transfer. This
voltage is used as a reference level for the differential signal amplifier.
shift register
The 512-bit shift register controls the transfer of charge from the pixels to the output stages and provides timing
signals for the NOCG. The serial input (SI) signal provides the input to the shift register and is shifted under direct
control of CLK out to the serial output (SO) on the 512th clock cycle. This SO pulse can then be used as the
SI pulse for the next device.
The output period is initiated by the presence of the SI input pulse coincident with a rising edge of CLK (see
Figures 1 and 2). The analog output voltage corresponds to the level of the first pixel after settling time (t_s) and
remains constant for a minimum time (t_v). A voltage corresponding to each succeeding pixel is available at each
rising edge of CLK. The output period of the device ends when it sees the rising edge of the 513th clock cycle,
at which time the output assumes the high-impedance state. Once the output period has been initiated by an
SI pulse, CLK must be allowed to complete 513 positive-going transitions in order to reset the internal logic to
a known state. To achieve minimum integration time, the SI pulse may be present on the 514th rising clock to
immediately restart the output phase.
sample-and-hold
The sample-and-hold signal generated by the NOCG holds the analog output voltage of each pixel constant until
the next pixel is clocked out. The signal is sampled while CLK is high and held constant while CLK is low.
nonoverlapping clock generators
The NOCG circuitry provides internal control signals for the sensor, including reset and pixel-charge sensing.
The signals are synchronous and are controlled by the outputs of the shift register.
initialization
Initialization of the sensor elements may be necessary on power up or during operation after any period of CLK
or SI inactivity exceeding the integration time. The initialization phase consists of 12 to 15 consecutively
performed output cycles and clears the pixels of any charge that may have accumulated during the inactive
period.
multiple-unit operation
Multiple-sensor devices can be connected together in a serial or parallel configuration. The serial connection
is accomplished by connecting analog outputs (AO) together and connecting the SO output of each sensor
device to the SI input of the next device. The SI signal is applied to only the first device. Each succeeding device
receives its SI input from the SO output of the preceding device. For m-cascaded devices, the SI pulse is applied
to the first device after every m × 512th positive-going CLK transition. A common clock signal is applied to all
the devices simultaneously. Parallel operation of multiple devices is accomplished by supplying CLK and SI
signals to all the devices simultaneously. The output of each device is then separately used for processing.
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