TPS7A3001-EP_15 Datasheet, PDF (3/25 Pages) Texas Instruments – –36V, –200mA, ULTRALOW-NOISE, NEGATIVE LINEAR REGULATOR

TPS7A3001-EP
www.ti.com
SBVS174 – OCTOBER 2011
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
T_J
–55°C to 125°C
PACKAGE
DGN
ORDERING INFORMATION⁽¹⁾
ORDERABLE PART
NUMBER
TPS7A3001MDGNTEP
TOP-SIDE
MARKING
PXCM
VID NUMBER
V62/11619-01XE
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Over operating free-air temperature range (unless otherwise noted).
Voltage
Current
Temperature
Electrostatic discharge rating
IN pin to GND pin
OUT pin to GND pin
OUT pin to IN pin
FB pin to GND pin
FB pin to IN pin
EN pin to IN pin
EN pin to GND pin
NR/SS pin to IN pin
NR/SS pin to GND pin
Peak output
Operating virtual junction, T_J
Storage, T_stg
Human body model (HBM)
Charged device model (CDM)
VALUE
MIN
MAX
–36
+0.3
–33
+0.3
–0.3
+36
–2
+0.3
–0.3
+36
–0.3
+36
–36
+36
–0.3
+36
–2
+0.3
Internally limited
–55
+135
–65
+150
1500
500
UNIT
V
V
V
V
V
V
V
V
V
°C
°C
V
V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
TPS7A3001
DGN
UNITS
8 PINS
θ_JA
θ_JC(top)
θ_JB
ψ_JT
ψ_JB
θ_JC(bottom)
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
69.3
40.3
39.0
°C/W
2.4
38.7
17.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011, Texas Instruments Incorporated
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