TPS53127_15 Datasheet, PDF (3/30 Pages) Texas Instruments – TPS53127 Dual Synchronous Step-Down Controller For Low Voltage Power Rails

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6 Pin Configuration and Functions
QFN Package
Top View
VO1 ₁
VFB1 2
GND 3
SS1 4
VFB2 5
VO2 6
18 ^TRIP1
17 ^VIN
16 ^VREG5
15 ^{V5 FILT}
14 ^SS2
13 ^TRIP2
TPS53127
SLVSA93A – MARCH 2010 – REVISED AUGUST 2014
TSSOP Package
Top View
DRVH1 1
VBST1 2
EN1 ³
VO1 ⁴
VFB1 ⁵
GND 6
SS1 ⁷
VFB2 8
VO2 9
EN2 10
VBST2 ₁₁
DRVH2 12
24 SW1
23 DRVL1
22 PGND1
21 TRIP1
20 VIN
19 ^VREG5
18 V5FILT
17 SS2
16 TRIP2
15 PGND2
14 DRVL2
13 SW2
NAME
VBST1,
VBST2
EN1, EN2
VO1, VO2
VFB1,
VFB2
GND
DRVH1,
DRVH2
SW1, SW2
DRVL1,
DRVL2
PGND1,
PGND2
TRIP1,
TRIP2
VIN
PIN
QFN
24
23, 8
24, 7
1, 6
2, 5
3
22, 9
21, 10
20, 11
19, 12
18, 13
17
V5FILT
15
VREG5
16
SS1, SS2
4,14
TSSOP
24
2, 11
3, 10
4, 9
5, 8
6
1, 12
24, 13
23, 14
22, 15
21, 16
20
18
19
7, 17
Pin Functions
I/O
DESCRIPTION
Supply input for high-side NFET driver. Bypass to SWx with a high-quality 0.1-
I
μF ceramic capacitor. An external schottky diode can be added from VREG5 if
forward drop is critical to drive the high-side FET.
I
Enable. Pull High to enable SMPS.
I
Output voltage inputs for on-time adjustment and output discharge. Connect
directly to the output voltage.
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
I
Signal ground pin. Connect to PGND1, PGND2 and system ground at a single
point.
O
High-side N-Channel MOSFET gate driver outputs. SWx referenced drivers
switch between SWx (OFF) and VBSTx (ON).
I/O
Switch node connections for both the high-side drivers and the over current
comparators.
O
Low-side N-Channel MOSFET gate driver outputs. PGND referenced drivers
switch between PGNDx (OFF) and VREG5 (ON).
Power ground connections for both the low-side drivers and the over current
I/O
comparators. Connect PGND1, PGND2 and GND strongly together near the
IC.
I
Over current threshold programming pin. Connect to GND with a resistor to
GND to set threshold for low-side R_DS(ON) current limit.
I
Supply Input for 5-V linear regulator. Bypass to GND with a minimum high-
quality 0.1-μF ceramic capacitor.
5-V supply input for the entire control circuitry except the MOSFET drivers.
I
Bypass to GND with a minimum high-quality 1.0-μF ceramic capacitor. V5FILT
is connected to VREG5 via an internal 10-Ω resistor.
Output of 5-V linear regulator and supply for MOSFET drivers. Bypass to GND
O
with a minimum high-quality 4.7-μF ceramic capacitor. VREG5 is connected to
V5FILT via an internal 10-Ω resistor.
O
Soft-start programming pin. Connect capacitor from SSx pin to GND to program
soft-start time.
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