TPA0142 Datasheet, PDF (3/30 Pages) Texas Instruments – 2-W STEREO AUDIO POWER AMPLIFIER WITH DC VOLUME CONTROL

TPA0142
2-W STEREO AUDIO POWER AMPLIFIER
WITH DC VOLUME CONTROL
SLOS248B – JUNE 1999 – REVISED MARCH 2000
AVAILABLE OPTIONS
PACKAGED DEVICE
TA
TSSOP†
(PWP)
– 40°C to 85°C
TPA0142PWP
† _{The PWP package is available taped and reeled. To order a taped and reeled part,}
add the suffix R to the part number (e.g., TPA0142PWPR).
Terminal Functions
TERMINAL
NAME
NO.
BYPASS
11
CLK
17
GND
LHPIN
LIN
LLINEIN
LOUT+
LOUT–
1, 12
13, 24
6
10
5
4
9
PCB ENABLE 2
PC-BEEP
PVDD
RHPIN
RIN
RLINEIN
ROUT+
ROUT–
SE/BTL
SHUTDOWN
VDD
VOLUME
14
7, 18
20
8
23
21
16
15
22
19
3
I/O
DESCRIPTION
Tap to voltage divider for internal mid-supply bias generator
I
If a 47-nF capacitor is attached, the TPA0142 generates an internal clock. An external clock can override
the internal clock input to this terminal.
Ground connection for circuitry. Connected to thermal pad
I Left channel headphone input, selected when SE/BTL is held high
I Common left input for fully differential input. AC ground for single-ended inputs
I Left channel line negative input, selected when SE/BTL is held low
O Left channel positive output in BTL mode and positive output in SE mode
O Left channel negative output in BTL mode and high-impedance in SE mode
If this terminal is high, the detection circuitry for PC-BEEP is overridden and passes PC-BEEP through the
I amplifier, regardless of its amplitude. If PCB ENABLE is floating or low, the amplifier continues to operate
normally.
I
The input for PC Beep mode. PC-BEEP is enabled when a > 1-V (peak-to-peak) square wave is input to
PC-BEEP or PCB ENABLE is high.
I Power supply for output stage
I Right channel headphone input, selected when SE/BTL is held high
I Common right input for fully differential input. AC ground for single-ended inputs
I Right channel line input, selected when SE/BTL is held low
O Right channel positive output in BTL mode and positive output in SE mode
O Right channel negative output in BTL mode and high-impedance in SE mode
I
Input MUX control input. When this terminal is held high, the LHPIN or RHPIN and SE output is selected.
When this terminal is held low, the LLINEIN or RLINEIN and BTL output are selected.
I When held low, this terminal places the entire device, except PC-BEEP detect circuitry, in shutdown mode.
I Analog VDD input supply. This terminal needs to be isolated from PVDD to achieve highest performance.
I
VOLUME detects the dc level at the terminal and sets the gain for 31 discrete steps covering a range of
20 dB to –40 dB for dc levels of 0.15 V to 3.54. When the dc level is over 3.54 V, the device is muted.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3