TLE4275QKVURQ1 Datasheet, PDF (3/22 Pages) Texas Instruments – 5-V LOW-DROPOUT VOLTAGE REGULATOR

TLE4275-Q1
www.ti.com
SLVS647H – AUGUST 2006 – REVISED MARCH 2013
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
V_I
V_O
I_I
I_O
T_J
T_stg
ESD
Input voltage range⁽²⁾
Output voltage range
Input current
Output current
Operating junction temperature range
Storage temperature range
Electrostatic discharge rating
IN
DELAY
OUT
RESET
DELAY
RESET
Human-body model (HBM)⁽³⁾
Machine model (MM)⁽⁴⁾
MIN
MAX UNIT
–42
45
V
–0.3
7
–1
16
V
–0.3
25
±2 mA
±5 mA
–40
150 °C
–65
150 °C
6000
V
400
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal.
(3) HBM ESD rating tested per JESD22-A114.
(4) MM ESD rating tested per JESD22-A115.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
V_I
Input voltage
T_J
Junction temperature
MIN
MAX UNIT
5.5
42 V
–40
150 °C
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
TLE4275-Q1
KTT
KVU
PWP
UNIT
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
5 PINS
28.8
43.1
0.8
3.7
0.7
0.2
5 PINS
40.3
31.8
17.2
2.8
17.1
0.7
20 PINS
39.3
22.7
19.1
0.6
18.9
1.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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