TLC32044C Datasheet, PDF (3/39 Pages) Texas Instruments – VOICE-BAND ANALOG INTERFACE CIRCUITS

TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
functional block diagram
SLAS017F – MARCH 1988 – REVISED MAY 1995
IN +
IN –
AUX IN +
AUX IN –
OUT +
OUT –
Filter
M
U
X
M
sin x/x
U
Correction
X
M
U
A/D
X
Receive Section
SERIAL
PORT
Filter
Internal
Voltage
Reference
D/A
Transmit Section
FSR
DR
EODR
MSTER CLK
SHIFT CLK
WORD/BYTE
DX
FSX
EODX
VCC ₊ VCC _– ANLG DTGL VDD
GND GND (Digital)
REF
RESET
TERMINAL
NAME
NO.
ANLG GND
17,18
AUX IN +
24
AUX IN –
23
DGTL GND
9
DR
5
DX
12
EODR
3
Terminal Functions
I/O
DESCRIPTION
Analog ground return for all internal analog circuits. Not internally connected to DGTL GND.
I Noninverting auxiliary analog input stage. AUX IN + can be switched into the bandpass filter and A/D
converter path via software control. If the appropriate bit in the control register is a 1, the auxiliary inputs
will replace the IN + and IN – inputs. If the bit is a 0, the IN + and IN – inputs will be used (see the AIC DX
data word format section).
I Inverting auxiliary analog input (see the above AUX IN + description).
Digital ground for all internal logic circuits. Not internally connected to ANLG GND.
O Data receive. DR is used to transmit the ADC output bits from the AIC to the TMS320 (SMJ320) serial port.
This transmission of bits from the AIC to the TMS320 (SMJ320) serial port is synchronized with the SHIFT
CLK signal.
I Data transmit. DX is used to receive the DAC input bits and timing and control information from the TMS320
(SMJ320). This serial transmission from the TMS320 (SMJ320) serial port to the AIC is synchronized with
the SHIFT CLK signal.
O End of data receive. (See the WORD/BYTE description and Serial Port Timing diagram.) During the
word-mode timing, EODR is a low-going pulse that occurs immediately after the 16 bits of A/D information
have been transmitted from the AIC to the TMS320 (SMJ320) serial port. EODR can be used to interrupt
a microprocessor upon completion of serial communications. Also, EODR can be used to strobe and enable
external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus
communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing,
EODR goes low after the first byte has been transmitted from the AIC to the TMS320 (SMJ320) serial port
and is kept low until the second byte has been transmitted. The DSP can use this low-going signal to
differentiate between the two bytes as to which is first and which is second. EODR does not occur after
secondary communication.
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