THS4031CDR Datasheet, PDF (3/47 Pages) Texas Instruments – 100-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS

www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
Null
1
IN−
2
−
8
6
3
IN+
+
OUT
Figure 1. THS4031 – Single Channel
THS4031
THS4032
SLOS224G – JULY 1999 – REVISED MARCH 2010
V_CC
1IN− ²
1IN+ ³
−8
+
1
1OUT
2IN− ⁶
5
2IN+
−
+
4
7
2OUT
−V_CC
Figure 2. THS4032 – Dual Channel
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Over operating free-air temperature range (unless otherwise noted).
V_CC
Supply voltage, V_CC+ to V_CC–
V_I
Input voltage
I_O
Output current
V_IO
Differential input voltage
Continuous total power dissipation
C-suffix
T_A
Operating free-air
temperature
I-suffix
M-suffix
T_J
Maximum junction temperature, (any condition)
Maximum junction temperature, continuous operation, long term reliability⁽²⁾
T_stg
Storage temperature
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package
Case temperature for 60 seconds, FK package
VALUE
UNIT
33
V
±V_CC
150
mA
±4
V
See Dissipation Ratings Table
0 to 70
–40 to 85
°C
–55 to 125
150
°C
130
°C
–65 to 150
°C
300
°C
300
°C
260
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device. Does not apply to the JG package or FK package.
DISSIPATION RATINGS TABLE
PACKAGE
D
DGN ⁽²⁾
JG
FK
q_JA
(°C/W)
167 ⁽¹⁾
58.4
119
87.7
q_JC
(°C/W)
38.3
4.7
28
20
T_A = 25°C,
POWER RATING
629 mW, T_J = 130°C, continuous
1.8 W, T_J = 130°C, continuous
1050 mW, T_J = 150°C, continuous
1375 mW, T_J = 150°C, continuous
(1) This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed High-K test PCB, the q_JA is 95°C/W with a
power rating at T_A = 25°C of 1.32 W.
(2) This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3-in. × 3-in. PC. For further information, refer to
Application Information section of this data sheet.
Copyright © 1999–2010, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): THS4031 THS4032