TAS5132 Datasheet, PDF (3/23 Pages) Texas Instruments – STEREO DIGITAL AMPLIFIER POWER STAGE

TAS5132
www.ti.com
SLES190 – DECEMBER 2006
GENERAL INFORMATION (continued)
MODE Selection Pins
MODE PINS
M3
M2
M1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PWM INPUT
OUTPUT CONFIGURATION
PROTECTION SCHEME
2N ⁽¹⁾ AD/BD modulation
Reserved
1N ⁽¹⁾ AD modulation
1N ⁽¹⁾ AD modulation
1N ⁽¹⁾ AD modulation
2 channels BTL output
2 channels BTL output
1 channel PBTL output
4 channels SE output
2N ⁽¹⁾ AD/BD modulation 2 channels BTL output
BTL mode ⁽²⁾
BTL mode ⁽²⁾
PBTL mode. Only PWM_A input is used.
Protection works similarly to BTL mode ⁽²⁾. Only
difference in SE mode is that OUT_X is Hi-Z
instead of a pulldown through internal pulldown
resistor.
Protection system work similarly to BTL mode
(2) _{(0, 0, 0); however the PWM input protection}
is disabled. Also, overcurrent detection will be
more sensitive and will latch if an error occurs.
Reserved
(1) The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific
mode.
(2) An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errors
like overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels.
Package Heat Dissipation Ratings⁽¹⁾
PARAMETER
R_θJC (°C/W)—2 BTL or 4 SE channels (8 transistors)
R_θJC (°C/W)—1 BTL or 2 SE channel(s) (4 transistors)
R_θJC (°C/W)—(1 transistor)
Pad area⁽²⁾
TAS5132DDV
1.4
2.6
8.7
15 mm²
(1) JC is junction-to-case, CH is case-to-heatsink.
(2) R_θCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The
R_θCH with this condition is 2.5°C/W for the DDV package.
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