SN74LV8153_08 Datasheet, PDF (3/16 Pages) Texas Instruments – SERIAL-TO-PARALLEL INTERFACE

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SN74LV8153
SERIALĆTOĆPARALLEL INTERFACE
SCLS555 − JUNE 2004
data transmission protocol
− The serial data should be sent as 2START-3ADDRESS-4DATA-1STOP. Two consecutive serial-data
frames transmit 8 bits of data. The first frame includes the lower four bits of data (D0-D3), and the
second frame includes the upper four bits (D4-D7).
− The three address bits (in the consecutive frame) must be the same as those in the first frame;
otherwise, the data will be dropped.
− The order of the two start bits must be 0, then 1 in any frame; otherwise, the data rate will not be
detected correctly. The period between the falling edge of the first start bit (ST0) and the rising edge of
the second start bit (ST1) is measured to generate an internal-clock synchronized data stream.
1st Frame
2nd Frame
ST0
A0 A1 A2 D0 D1 D2 D3
ST0
A0 A1 A2 D4 D5 D6 D7
ST1
SP
ST1
SP
Example of Serial-Data Format
DATA
ST0
ST0
A0 A1 A2 D0 D1 D2 D3
A0 A1 A2 D4 D5 D6 D7
ST1
SP
ST1
SP
Internal Clock
Y0−Y7
SOUT
Timing Chart
(1)Internal _{clock cannot be observed.}
(2)D0 _{is LSB and D7 is MSB. The data stream should be LSB first.}
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