SN74LV4046A Datasheet, PDF (3/12 Pages) Texas Instruments – HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO

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SN74LV4046A
HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP
WITH VCO
SCES656A – FEBRUARY 2006 – REVISED FEBRUARY 2006
Electrical Specifications
PARAMETER
VCO
V_IH High-level input voltage INH
V_IL
Low-level input voltage INH
V_OH
High-level
output voltage
VCO_OUT
CMOS
TTL
V_OL
Low-level
output voltage
VCO_OUT
CMOS
TTL
C1A, C1B
(test purposes only)
I_I
Input leakage current INH, VCO_IN
R1 range⁽¹⁾
R2 range⁽¹⁾
C1 capacitance range
Operating voltage
range
VCO_IN
Phase Comparator
V_IH
DC-coupled high-level
input voltage
SIG_IN,
COMP_IN
V_IL
DC-coupled low-level input voltage
SIG_IN,
COMP_IN
V_OH
High-level
output voltage
PCP_OUT,
PCN_OUT
CMOS
TTL
V_OL
Low-level
output voltage
PCP_OUT,
PCN_OUT
CMOS
TTL
I_I
Input leakage current
I_OZ
3-state off-state current
R_I
Input resistance
Demodulator
SIG_IN,
COMP_IN
PC2_OUT
SIG_IN,
COMP_IN
R_S
Resistor range
V_OFF Offset voltage VCO_IN to V_DEM
I_CC
Quiescent device current
TEST CONDITIONS
V_I (V)
I_O (mA)
V_CC (V)
MIN TYP
MAX UNIT
V_IL or V_IH
V_IL or V_IH
V_CC or GND
–0.05
–12
0.05
12
12
Over the range specified
for R1 for linearity⁽²⁾
3 to 3.6
4.5 to 5.5
3 to 5.5
4.5 to 5.5
3 to 3.6
4.5 to 5.5
4.5 to 5.5
3 to 3.6
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
5.5
3 to 5.5
3 to 4.5
3 to 3.6
4.5 to 5.5
3 to 3.6
4.5 to 5.5
V_CC × 0.7
V_CC × 0.7
V_CC – 0.1
V_CC – 0.1
3.8
3
3
40
40
1.1
1.1
V
V_CC × 0.3 _V
V_CC × 0.3
V
0.1
0.1
0.55 ^V
0.65
±1 µA
50 kΩ
50 kΩ
No Limit pF
1.9
V
3.2
V_IL or V_IH
V_IL or V_IH
–0.05
–6
–12
0.02
4
V_CC or GND
V_IL or V_IH
V_I at self-bias operating
point, V_I = 0.5 V
3 to 3.6
4.5 to 5.5
3 to 3.6
4.5 to 5.5
3 to 5.5
3 to 3.6
4.5 to 5.5
3 to 3.6
4.5 to 5.5
4.5 to 5.5
V_CC × 0.7
V_CC × 0.7
V_CC – 0.1
2.48
3.8
V_CC × 0.3 _V
V_CC × 0.3
V
0.1
0.1 _V
0.4
3 to 3.6
4.5 to 5.5
3 to 5.5
3
4.5
±11
µA
±29
±5 µA
800
kΩ
250
R_S > 300 kΩ, Leakage
current can influence
V_DEMOUT
V_I = V_VCOIN = V_CC/2,
Values taken over R_S
range
Pins 3, 5, and 14 at V_CC,
Pin 9 at GND, I_I at pins 3
and 14 to be excluded
3 to 3.6
4.5 to 5.5
3 to 3.6
4.5 to 5.5
5.5
50
50
±30
±20
300
kΩ
300
mV
50 µA
(1) The value for R1 and R2 in parallel should exceed 2.7 kΩ.
(2) The maximum operating voltage can be as high as V_CC – 0.9 V; however, this may result in an increased offset voltage.
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