SN74GTL2006 Datasheet, PDF (3/10 Pages) Texas Instruments – 13-BIT GTL-/GTL/GTL+ TO LVTTL TRANSLATOR

logic symbol
GTL VREF
1
1AO
2
LVTTL Outputs
2AO
3
5A
4
(Open Drain)
LVTTL I/Os
6A
5
(Open Drain)
LVTTL Input 8AI
6
GTL Input 11BI
7
LVTTL I/O 11A
8
(Open Drain)
GTL Input 9BI
9
LVTTL
Outputs
3AO
10
4AO
11
SN74GTL2006
13ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR
SCES619 – DECEMBER 2004
SN74GTL2006
Delay
Delay
27
1BI
GTL
26
2BI ^Inputs
25
7BO1
24
7BO2
GTL
23
8BO
Outputs
22
11BO
21
5BI
20
6BI
GTL
19
Inputs
3BI
18
4BI
10AI1
12
LVTTL
Inputs
13
10AI2
17
10BO1 _GTL
16
Outputs
10BO2
15
9AO LVTTL Output
NOTE A: The enable on 7BO1/7BO2 includes a delay that prevents a transient conditon (where 5BI/6BI go from low to high, and the low to high
on 5A/6A lags up to 100 ns) from causing a low glitch on the 7BO1/7BO2 outputs.
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