SN74CBT16210 Datasheet, PDF (3/4 Pages) Texas Instruments – 20-BIT FET BUS SWITCH

SN74CBT16210
20-BIT FET BUS SWITCH
SCDS033C – APRIL 1997 – REVISED MAY 1998
switching characteristics over recommended operating free-air temperature range, C_L = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd†
FROM
(INPUT)
A or B
TO
(OUTPUT)
B or A
VCC = 4 V
MIN MAX
0.35
VCC = 5 V
± 0.5 V
MIN MAX
0.25
UNIT
ns
ten
OE
A or B
9.3 3.3 8.6 ns
tdis
OE
A or B
7.1 2.8 7.9 ns
† _{The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when}
driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
7V
S1
Open
GND
LOAD CIRCUIT
Input
1.5 V
3V
1.5 V
0V
tPLH
tPHL
Output
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
1.5 V
VOL
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7V
Open
Output
Control
(low-level
enabling)
tPZL
1.5 V
3V
1.5 V
0V
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
tPZH
tPLZ
1.5 V
tPHZ
1.5 V
3.5 V
VOL + 0.3 V
VOL
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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