SN74AUP1T87 Datasheet, PDF (3/11 Pages) Texas Instruments – LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, 2-INPUT EXCLUSIVE-NOR GATE

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Static-Power Consumption
(µA)
100%
Dynamic-Power Consumption
(pF)
100%
80%
80%
60%
40%
3.3-V
Logic^†
60%
40%
L³V^.3C^-V
Logic^†
20%
0%
AUP
20%
0%
† _{Single, dual, and triple gates}
AUP
Figure 1. AUP – The Lowest-Power Family
3.3 V
SN74AUP1T87
SCES806 – APRIL 2010
Switching Characteristics
at 25 MHz^†
3.5
3
2.5
2 Input
1.5
1
Output
0.5
0
−0.5 _{0 5 10 15 20 25 30 35 40 45}
Time − ns
† _{AUP1G08 data at CL = 15 pF}
Figure 2. Excellent Signal Integrity
3.3 V
1.8-V
System
V_IH = 1.19 V
V_IL = 0.5 V
3.3-V
System
2.5-V
System
V_IH = 1.19 V
V_IL = 0.5 V
3.3-V
System
2.5 V
2.5 V
1.8-V
System
V_IH = 1.10 V
V_IL = 0.35 V
2.5-V
System
3.3-V
System
V_IH = 1.10 V
V_IL = 0.35 V
Figure 3. Typical Design Examples
3.3 V
2.5-V
System
1.8-V
System
3.3-V
System
V_T+ max = V_IH min = 1.19 V
V_T− min = V_IL max = 0.5 V
Input Switching Waveform
Output Switching Waveform
Figure 4. Switching Thresholds for 1.8-V to 3.3-V Translation
V_OH min
V_OL max
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