SN74AS8003 Datasheet, PDF (3/8 Pages) Texas Instruments – DUAL 2-INPUT POSITIVE-NAND GATE

From Output
Under Test
CL = 50 pF
(see Note A)
SN74AS8003
DUAL 2-INPUT POSITIVE-NAND GATE
SDAS305 – OCTOBER 1999
PARAMETER MEASUREMENT INFORMATION
VCC
7V
RL = R1 = R2
S1
Test
Point
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
Test
Point
500 Ω
LOAD CIRCUIT
FOR BI-STATE TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
Timing
Input
tsu
Data
Input
1.3 V
th
1.3 V
1.3 V
3.5 V
0.3 V
3.5 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
High-Level
Pulse
Low-Level
Pulse
1.3 V
tw
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
3.5 V
0.3 V
Output
Control
(low-level
enabling)
tPZL
Waveform 1
S1 Closed
(see Note B)
1.3 V
1.3 V
1.3 V
tPLZ
3.5 V
0.3 V
≈3.5 V
0.3 V
VOL
tPZH
tPHZ
Waveform 2
S1 Open
(see Note B)
1.3 V
VOH
0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
Input
1.3 V
tPLH
1.3 V
3.5 V
0.3 V
tPHL
In-Phase
Output
1.3 V
VOH
1.3 V
VOL
tPHL
tPLH
Out-of-Phase
Output
(see Note C)
1.3 V
VOH
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3