SN65MLVD2 Datasheet, PDF (3/17 Pages) Texas Instruments – SINGLE M-LVDS RECEIVERS

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SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION⁽¹⁾
PART NUMBER
SN65MLVD2DRBT
SN65MLVD2DRBR
SN65MLVD3DRBT
SN65MLVD3DRBR
FUNCTION
M-LVDS Type 1 Receiver
M-LVDS Type 1 Receiver
M-LVDS Type 2 Receiver
M-LVDS Type 2 Receiver
PART MARKING
MF2
MF2
MF3
MF3
PACKAGE / CARRIER
8-Pin SON / Small Tape and Reel
8-Pin SON / Tape and Reel
8-Pin SON / Small Tape and Reel
8-Pin SON / Tape and Reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) ⁽¹⁾
VALUE
UNIT
V_CC
Supply voltage range⁽²⁾
Input voltage range
RE
A or B
–0.5 to 4
V
–0.5 to 4
V
–1.8 to 4
V
Output voltage range
R
–0.3 to 4
V
Electrostatic discharge
Human-body model⁽³⁾
Machine model⁽⁴⁾
All other pins
A, B
All pins
±7
kV
±9
±200
V
Field-induced-charged-device model⁽⁵⁾ All pins
±2
kV
Continuous power dissipation
See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A. Bus pin stressed with respect to a common connection of GND
and V_CC.
(4) Tested in accordance with JEDEC Standard 22 Test Method A115-A.
(5) Tested in accordance with EIA-JEDEC JESD22-C101C.
PACKAGE DISSIPATION RATINGS⁽¹⁾
PACKAGE
8-SON DRB
PCB TYPE
Low-K
High-K
T_A≤ 25°C
POWER RATING
280 mW
662 mW
DERATING FACTOR⁽²⁾
ABOVE T_A = 25°C
2.80 mW/°C
6.62 mW/°C
T_A = 85°C
POWER RATING
112 mW
264 mW
(1) The thermal dissipations are in the consideration of soldering down the powerPAD without via on each type of boards.
(2) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
THERMAL CHARACTERISTICS
PARAMETER
θ_JB Junction-to-board thermal resistance
θ_JC Junction-to-case thermal resistance
P_D
Device power dissipation
TEST CONDITIONS
RE at 0 V, C_L = 15 pF, V_ID = 400 mV, 125 MHz
MIN TYP MAX UNIT
89
° C/W
98
° C/W
90 mW
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