SN65LVDM320 Datasheet, PDF (3/32 Pages) Texas Instruments – HIGH-SPEED DIFFERENTIAL 8-BIT REGISTERED TRANSCEIVER

SN65LVDM320
Table 2. Pin Descriptions
PIN
NAME
NO.
AGND
36, 44, 54,
58, 62
1BY–8BY &
1BZ–8BZ
64 & 63,
60 & 59,
56 & 55,
52 & 51,
46 & 45,
42 & 41,
38 & 37,
34 & 33
CLK/LEBA
18
CLK/LEAB
14
1DA–8DA
1, 3, 7, 9,
21, 25, 29,
31
DGND
5, 11, 15,
19, 23, 27
ENR
39
IMODE1
50,
IMODE2
49
LPBK
48
OEA
47
OEB
40
OMODE1,
13,
OMODE2
17
RA
2, 4, 8, 10,
22, 26, 30,
32
VCC
6, 12, 16,
20, 24, 28,
35, 43, 53,
57, 61
DESCRIPTION
Analog (B-side) ground
Differential I/O pair
B-side to A-side clock input or latch enable
A-side to B-side clock input or latch enable
Single-ended input
Digital (A-side) ground
Receiver differential data enable
B-side to A-side buffer, flip-flop, or latch mode control and
bus loopback control (see Table 3)
A-side loopback enable
A-side output enable
B-side output enable
A-side to B-side buffer, flip-flop, or latch mode control and
bus loopback control (see Table 3)
Single-ended output
Supply voltage
SLLS462 – AUGUST 2001
pin assignments
SN65LVDM320DGG
(Marked as LVDM320)
(TOP VIEW)
1DA ₁
1RA ₂
2DA ₃
2RA ₄
DGND ₅
VCC ₆
3DA ₇
3RA ₈
4DA ₉
4RA ₁₀
DGND ₁₁
VCC ₁₂
OMODE1 ₁₃
CLK/LEAB ₁₄
DGND ₁₅
VCC ₁₆
OMODE2 ₁₇
CLK/LEBA ₁₈
DGND ₁₉
VCC ₂₀
5DA ₂₁
5RA ₂₂
DGND 23
VCC 24
6DA 25
6RA 26
DGND 27
VCC 28
7DA 29
7RA 30
8DA 31
8RA 32
64 ^1BY
63 ^1BZ
62 ^AGND
61 ^VCC
60 ^2BY
59 ^2BZ
58 ^AGND
57 ^VCC
56 ^3BY
55 ^3BZ
54 ^AGND
53 ^VCC
52 ^4BY
51 ^4BZ
50 ^IMODE1
49 ^IMODE2
48 ^LPBK
47 ^OEA
46 ^5BY
45 ^5BZ
44 ^AGND
43 ^VCC
42 6BY
41 6BZ
40 OEB
39 ENR
38 7BY
37 7BZ
36 AGND
35 VCC
34 8BY
33 8BZ
Table 3. IMODE Logic
Table 4. OMODE Logic
IMODE1 IMODE2
MODE FUNCTION
(B SIDE TO A SIDE)
IMODE1 IMODE2
0
0
Buffer
0
0
0
1
Flip-Flop
0
1
1
0
Latch
1
0
1
1
Bus loopback^†
1
1
† _{All IMODE and OMODE pins must be high for the differential bus loopback latch mode.}
MODE FUNCTION
(A SIDE TO B SIDE)
Buffer
Flip-Flop
Latch
Bus loopback^†
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