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PTH05060W_15 Datasheet, PDF (3/19 Pages) Texas Instruments – 10-A, 5-V Input Non-Isolated Wide-Output Adjust Power Module
PTH05060W —5-V Input
10-A, 5-V Input Non-Isolated
Wide-Output Adjust Power Module
SLTS216B – MAY 2003 – REVISED DECEMBER 2003
Environmental & Absolute Maximum Ratings (Voltages are with respect to GND)
Characteristics
Symbols
Conditions
Min
Typ
Track Input Voltage
Operating Temperature Range
Solder Reflow Temperature
Storage Temperature
Mechanical Shock
Mechanical Vibration
Weight
Flammability
Vtrack
Ta
Treflow
Ts
—
—
–0.3
—
Over Vin Range
Surface temperature of module body or pins
–40 (i)
—
—
–40
—
Per Mil-STD-883D, Method 2002.3
1 msec, ½ Sine, mounted
—
200
Mil-STD-883D, Method 2007.2
Suffix H —
20
20-2000 Hz
Suffix S —
20
—
3.7
Meets UL 94V-O
Max
Vin + 0.3
85
235 (ii)
125
—
—
—
—
Units
V
°C
°C
°C
G’s
G’s
grams
Notes: (i) For operation below 0 °C the external capacitors must bave stable characteristics. use either a low ESR tantalum, Os-Con, or ceramic capacitor.
(ii) During reflow of SMD package version do not elevate peak temperature of the module, pins or internal components above the stated maximum.
Specifications (Unless otherwise stated, Ta =25 °C, Vin =5 V, Vo =3.3 V, Cin =330 µF, Cout =0 µF, and Io =Iomax)
PTH05060W
Characteristics
Symbols
Conditions
Min
Typ
Max
Units
Output Current
Io
0.8 V ≤ Vo ≤ 3.6 V,
60 °C, 200 LFM airflow 0
25 °C, natural convection 0
—
—
10 (1)
10 (1)
A
Input Voltage Range
Set-Point Voltage Tolerance
Temperature Variation
Line Regulation
Load Regulation
Total Output Variation
Efficiency
Vo Ripple (pk-pk)
Over-Current Threshold
Transient Response
Margin Up/Down Adjust
Margin Input Current (pins 9 /10)
Track Input Current (pin 8)
Track Slew Rate Capability
Under-Voltage Lockout
Inhibit Control (pin3)
Input High Voltage
Input Low Voltage
Input Low Current
Vin
Vo tol
∆Regtemp
∆Regline
∆Regload
∆Regtot
η
Vr
Io trip
ttr
∆Vtr
∆Vo margin
IIL margin
IIL track
dVtrack/dt
UVLO
VIH
VIL
IIL inhibit
Over Io range
–40 °C <Ta < +85 °C
Over Vin range
Over Io range
Includes set-point, line, load,
–40 °C ≤ Ta ≤ +85 °C
Io =7 A
RSET = 698 Ω Vo = 3.3 V
RSET = 2.21 kΩ Vo = 2.5 V
RSET = 4.12 kΩ Vo = 2.0 V
RSET = 5.49 kΩ Vo = 1.8 V
RSET = 8.87 kΩ Vo = 1.5 V
RSET = 17.4 kΩ Vo = 1.2 V
RSET = 36.5 kΩ Vo = 1.0 V
20 MHz bandwidth
Reset, followed by auto-recovery
1 A/µs load step, 50 to 100 % Iomax,
Cout =330 µF
Recovery Time
Vo over/undershoot
Pin to GND
Pin to GND
Cout ≤ Cout(max)
Vin increasing
Vin decreasing
Referenced to GND
Pin to GND
4.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.4
Vin –0.5
–0.2
—
—
—
±0.5
±10
±12
—
94
92
91
90
89
86
85
25
20
70
100
±5
– 8 (3)
—
—
4.3
3.7
—
—
–130
5.5
±2 (2)
—
—
—
±3 (2)
—
—
—
—
—
—
—
—
—
V
%Vo
%Vo
mV
mV
%Vo
%
mVpp
A
—
—
—
—
–130 (4)
1
4.45
—
µSec
mV
%
µA
µA
V/ms
V
Open (4)
0.6
V
—
µA
Input Standby Current
Switching Frequency
External Input Capacitance
External Output Capacitance
Iin inh
ƒs
Cin
Cout
Inhibit (pin 3) to GND, Track (pin 8) open
Over Vin and Io ranges
Capacitance value
non-ceramic
ceramic
—
275
330 (5)
0
0
10
300
—
330 (6)
—
—
mA
325
kHz
—
µF
5,500 (7)
300
µF
Equiv. series resistance (non-ceramic)
4 (8)
—
—
µF
Reliability
MTBF
Per Bellcore TR-332
50 % stress, Ta =40 °C, ground benign
5.7
—
—
106 Hrs
Notes: (1) See SOA curves or consult factory for appropriate derating.
(2) The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a tolerance of 1 %
with 100 ppm/°C or better temperature stability.
(3) A small low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.
(4) This control pin has an internal pull-up to the input voltage Vin. If it is left open-circuit the module will operate when input power is applied. A small
low-leakage (<100 nA) MOSFET is recommended for control. For further information, consult the related application note.
(5) A 330 µF input capacitor is required for proper operation. The capacitor must be rated for a minimum of 500 mA rms of ripple current.
(6) An external output capacitor is not required for basic operation. Adding 330 µF of distributed capacitance at the load will improve the transient response.
(7) This is the calculated maximum. The minimum ESR limitation will often result in a lower value. Consult the application notes for further guidance.
(8) This is the typcial ESR for all the electrolytic (non-ceramic) output capacitance. Use 7 mΩ as the minimum when using max-ESR values to calculate.
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