PTB48540 Datasheet, PDF (3/12 Pages) Texas Instruments – 10-W Power-Over-Ethernet Isolated Power Module Assembly

PTB48540 Series
10-W Power-Over-Ethernet Isolated
Power Module Assembly
SLTS224B – APRIL 2004 – REVISED JULY 2004
Specifications (Unless otherwise stated, T_a =25°C, V_in =48V ⁽¹⁾, and I_o =I_omax)
PTB48540 SERIES
Characteristic
Symbol
Conditions
Min
Typ
Max
Units
Output Current
Input Voltage Range
Set Point Voltage Tolerance
Temperature Variation
Line Regulation
Load Regulation
Total Output Voltage Variation
Efficiency
V_o Ripple (pk-pk)
Transient Response
Output Voltage Adjust
Current Limit Threshold
Switching Frequency
Under-Voltage Lockout
Output Inhibit (Pin 13)
Input High Voltage
Input Low Voltage
Input Low Current
Standby Input Current
External Output Capacitance
Internal Input Capacitance
Detection Resistance
Classification Current
Operating Temperature Range
Over Temperature Protection
Isolation Voltage
Capacitance
Resistance
Solder Reflow Temperature
Storage Temperature
Reliability
Mechanical Shock
Mechanical Vibration
Weight
I_o
V_in
V_o tol
Reg_temp
Reg_line
Reg_load
∆V_otot
η
V_r
t_tr
∆V_tr
V_adj
I_lim
ƒ_s
UVLO
V_IH
V_IL
I_IL
I_in standby
C_out
C_in
R_detect
I_class
T_a
OTP
T_reflow
T_s
MTBF
—
—
—
Over V_in range
Over I_o Range
PTB48540A (5 V)
PTB48540B (3.3 V)
PTB48540C ( 12 V)
–40 ≤T_a ≤ +85 °C, I_o =I_omin
Over V_in range
Over I_o range
Includes set-point, line, load,
–40 ≤T_a ≤ +85 °C
PTB48540C (12 V)
PTB48540A (5 V)
PTB48540B (3.3 V)
20 MHz bandwidth
1 A/µs load step, 50 % to 100 % I_omax
V_o over/undershoot
V_o ≤ 5 V
V_o =12 V
V_in = 42 V, ∆V_o = –1 %
Over V_in range
V_in rising
V_in falling
Referenced to Input Ref (pin 4)
pins 13 & 4 connected
V_in < UVLO threshold
V_in > UVLO threshold
2.7 V ≤ V_in ≤ 10.1 V
14.5 V ≤ V_in ≤ 20.5 V
Over V_in range
Measured at pin 7
Input–output
V_o ≤ 5 V
V_o = 12 V
Threshold
Hysterisis
Surface temperature of module body or pins
—
Per Bellcore TR-332
50 % stress, T_a =40 °C, ground benign
Per Mil-Std-883D, method 2002.3,
1 mS, half-sine, mounted to a fixture
Mil-Std-883D, Method 2007.2
20-2000 Hz, soldered to PC
Pkg EUP
Pkg EUQ
—
0.1 ⁽²⁾
0.1 ⁽²⁾
0.1 ⁽²⁾
36
—
—
—
—
—
—
—
—
—
—
—
—
—
—
200
—
30
4.5
–0.2
—
—
0 ⁽⁴⁾
0 ⁽⁴⁾
0.05
5
23.75
2
–40
135
—
1500
—
10
—
–40
4
—
—
—
—
—
—
—
—
±1
±0.2
±1
±5
±1.5
85
82
79
50
100
±150
±200
±10
150
300
40
32
—
—
–2
1
—
—
0.1
7
24.9 ⁽⁵⁾
2.5 ⁽⁶⁾
—
—
20
—
1,100
—
—
—
—
500
20
7.5
12
2
3
0.85
57 ⁽¹⁾
±2
—
—
—
±3
—
—
—
—
—
—
—
—
—
400
42
—
Open ⁽³⁾
+0.8
—
—
1000
330
0.12
—
26.25
3
+85 ⁽⁷⁾
—
—
—
—
—
235 ⁽⁸⁾
+125
—
—
—
—
—
A
VDC
%V_o
%V_o
mV
mV
%V_o
%
mV_pp
µs
mV
%V_o
%I_omax
kHz
V
V
mA
mA
µF
µF
kΩ
mA
°C
°C
V
pF
MΩ
°C
°C
10⁶ Hrs
G’s
G’s
grams
Flammability
—
Materials meet UL 94V-0
Notes: (1) The input voltage Vin is applied and measured between ‘Data Line A’ (pin 10) and ‘Data Line B’ (pin 9), or between ‘Spare Line A’ (pin 8) and ‘Spare
Line B (pin 7). These inputs accept either polarity.
(2) The DC/DC converter will operate at no load with reduced specifications.
(3) The Output Inhibit (pin 13) is referenced to ‘Input Ref ’ (pin 4) and has an internal pull-up. If it is left open circuit the converter will operate when
input power is applied. The open-circuit voltage is typically 5 V. Refer to the application notes for interface considerations.
(4) An output capacitor is not required for proper operation.
(5) This is the default for a “Valid Device” PD detection signature.
(6) This is the default for a “Class 0” PD classification signature.
(7) See Safe Operating Area curves or contact the factory for the appropriate derating.
(8) During the reflow of the SMD package version do not elevate the peak temperature of the module, pins, or internal components above the stated maximum.
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