LP2986ILD-3.3 Datasheet, PDF (3/26 Pages) Texas Instruments – Micropower, 200 mA Ultra Low-Dropout Fixed or Adjustable Voltage Regulator

LP2986
www.ti.com
SNVS137H – MARCH 1999 – REVISED APRIL 2013
Absolute Maximum Ratings⁽¹⁾⁽²⁾
Storage Temperature Range
Operating Junction Temperature Range
Lead Temperature (Soldering, 5 seconds)
ESD Rating⁽³⁾
Power Dissipation⁽⁴⁾
Input Supply Voltage (Survival)
Input Supply Voltage (Operating)
Shutdown Pin
Feedback Pin
Output Voltage (Survival)⁽⁵⁾
I_OUT (Survival)
Input-Output Voltage (Survival)⁽⁶⁾
−65°C to +150°C
−40°C to +125°C
260°C
2 kV
Internally Limited
−0.3V to +16V
2.1V to +16V
−0.3V to +16V
−0.3V to +5V
−0.3V to +16V
Short Circuit Protected
−0.3V to +16V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device outside of its rated operating conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The ESD rating of the Feedback pin is 500V. The ESD rating of the V_IN pin is 1kV and the Tap pin is 1.5 kV.
(4) The maximum allowable power dissipation is a function of the maximum junction temperature, T_J(MAX), the junction-to-ambient thermal
resistance, θ_J−A, and the ambient temperature, T_A. The maximum allowable power dissipation at any ambient temperature is calculated
using:
The value of θ_J−A for the SOIC-8 package is 160°C/W, and the VSSOP-8 package is 200°C/W. The value
θ_J−A for the WSON package is specifically dependent on PCB trace area, trace material, and the number of layers and thermal vias. For
improved thermal resistance and power dissipation for the WSON package, refer to Application Note AN-1187. Exceeding the maximum
allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.
(5) If used in a dual-supply system where the regulator load is returned to a negative supply, the LM2986 output must be diode-clamped to
ground.
(6) The output PNP structure contains a diode between the V _IN and V_OUT terminals that is normally reverse-biased. Forcing the output
above the input will turn on this diode and may induce a latch-up mode which can damage the part (see Application Hints).
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