DRV8836 Datasheet, PDF (3/16 Pages) Texas Instruments – DUAL LOW VOLTAGE H-BRIDGE IC

DRV8836
www.ti.com
SLVSB17 – MARCH 2012
Table 1. TERMINAL FUNCTIONS
NAME
PIN
POWER AND GROUND
GND
6
VCC
1
CONTROL
nSLEEP
12
MODE
11
AIN1/APHASE
10
AIN2/AENBL
9
BIN1/BPHASE
8
BIN2/BENBL
7
OUTPUT
AOUT1
2
AOUT2
3
BOUT1
4
BOUT2
5
I/O ⁽¹⁾
-
-
DESCRIPTION
Device ground
Device and motor supply
I
Sleep input
I
Input mode select
I
Bridge A input 1/PHASE input
I
Bridge A input 2/ENABLE input
I
Bridge B input 1/PHASE input
I
Bridge B input 2/ENABLE input
O
Bridge A output 1
O
Bridge A output 2
O
Bridge B output 1
O
Bridge B output 2
EXTERNAL COMPONENTS
OR CONNECTIONS
Bypass to GND with a 0.1-μF (minimum)
ceramic capacitor.
Active low places part in low-power sleep state.
Internal pulldown resistor
Logic low selects IN/IN mode.
Logic high selects PH/EN mode.
Internal pulldown resistor.
IN/IN mode: Logic high sets AOUT1 high.
PH/EN mode: Sets direction of H-bridge A.
Internal pulldown resistor.
IN/IN mode: Logic high sets AOUT2 high.
PH/EN mode: Logic high enables H-bridge A.
Internal pulldown resistor.
IN/IN mode: Logic high sets BOUT1 high.
PH/EN mode: Sets direction of H-bridge B.
Internal pulldown resistor.
IN/IN mode: Logic high sets BOUT2 high.
PH/EN mode: Logic high enables H-bridge B.
Internal pulldown resistor.
Connect to motor winding A
Connect to motor winding B
(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
DSS PACKAGE
(TOP VIEW)
VCC 1
12 nSLEEP
AOUT1 2
11 MODE
AOUT2 3
GND
10 AIN1 / APHASE
BOUT1 4 ^(PPAD) 9 AIN2 / AENBL
BOUT2 5
8 BIN1 / BPHASE
GND 6
7 BIN2 / BENBL
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Product Folder Link(s): DRV8836
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