DAC3282 Datasheet, PDF (3/49 Pages) Texas Instruments – 16-Bit, 625 MSPS, 2x Interpolating, Dual-Channel Digital-to-Analog Converter (DAC)

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PINOUT
DAC3282
SLAS646 – DECEMBER 2009
CLKVDD18 1
DACVDD18 2
DACCLKP 3
DACCLKN 4
GND 5
OSTRP 6
OSTRN 7
DIGVDD18 8
D7P 9
D7N 10
D6P 11
D6N 12
DAC3282
RGZ Package
48-QFN 7x7mm
(Top View )
36 RESETB
35 DACVDD18
34 ALARM_SDO
33 SDENB
32 SCLK
31 SDIO
30 TXENABLE
29 DIGVDD18
28 D0N
27 D0P
26 D1N
25 D1P
PIN FUNCTIONS
PIN
I/O
NAME
NO.
DESCRIPTION
AVDD33
37, 40, 42,
45, 48
I
Analog supply voltage. (3.3 V)
1.8V CMOS output for ALARM condition. The ALARM output functionality is defined through the
ALARM_SDO
34
O
CONFIG6 register. Default polarity is active low, but can be changed to active high via CONFIG0
alarm_pol control bit. Optionally, it can be used as the uni-directional data output in 4-pin serial
interface mode (CONFIG 23 sif4_ena = ‘1’).
BIASJ
43
O Full-scale output current bias. For 20mA full-scale output current, connect a 960 Ω resistor to GND.
CLKVDD18
1
I
Internal clock buffer supply voltage. (1.8 V)
It is recommended to isolate this supply from DACVDD18 and DIGVDD18.
D[7..0]P
LVDS positive input data bits 0 through 7. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two
data transfers per DATACKP/N clock cycle. Dual channel 16-bit data is transferred byte-wide on this
9, 11, 13,
single 8-bit data bus using FRAMEP/N as a frame strobe indicator.
15, 21, 23, I
25, 27
D7P is most significant data bit (MSB) – pin 9
D0P is least significant data bit (LSB) – pin 27
The order of the bus can be reversed via CONFIG19 rev bit.
D[7..0]N
10, 12, 14,
LVDS negative input data bits 0 through 15. (See D[7:0]P description above)
16, 22, 24, I
D7N is most significant data bit (MSB) – pin 10
26, 28
D0N is least significant data bit (LSB) – pin 28
Copyright © 2009, Texas Instruments Incorporated
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