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CD54ACT74 Datasheet, PDF (3/10 Pages) Texas Instruments – DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET | |||
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CD54ACT74, CD74ACT74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS321 â DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN MAX
â55°C to
125°C
MIN MAX
â40°C to
85°C
MIN MAX
UNIT
VOH
VI = VIH or VIL
VOL
II
ICC
DICCâ¡
VI = VIH or VIL
VI = VCC or GND
VI = VCC or GND,
VI = VCC â 2.1 V
IOH = â50 µA
IOH = â24 mA
IOH = â50 mAâ
IOH = â75 mAâ
IOL = 50 µA
IOL = 24 mA
IOL = 50 mAâ
IOL = 75 mAâ
IO = 0
4.5 V
4.5 V
5.5 V
5.5 V
4.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
4.5 V to
5.5 V
4.4
4.4
4.4
3.94
3.7
3.8
V
3.85
3.85
0.1
0.1
0.1
0.36
0.5
0.44
V
1.65
1.65
±0.1
±1
±1 µA
4
80
40 µA
2.4
3
2.8 mA
Ci
10
10
10 pF
â Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-⦠transmission-line drive capability at 85°C and 75-⦠transmission-line drive capability at 125°C.
â¡ Additional quiescent supply current per input pin, TTL inputs high, 1 unit load
ACT INPUT LOAD TABLE
INPUT
Data
PRE or CLR
CLK
UNIT LOAD
0.53
0.58
1
Unit load is âICC limit specified in
electrical characteristics table
(e.g., 2.4 mA at 25°C).
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time
th
Hold time
trec
Recovery time, before CLKâ
PRE or CLR low
CLK
Data
PRE or CLR inactive
Data after CLKâ
CLRâ or PREâ
â55°C to
125°C
MIN MAX
85
5
5.7
4
0
2.7
â40°C to
85°C
MIN MAX
97
4.4
5
3.5
0
2.4
UNIT
MHz
ns
ns
ns
ns
ns
⢠POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
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