BQ4287 Datasheet, PDF (3/8 Pages) Texas Instruments – Real-Time Clock Module With NVRAM Control

bq4287
Power-Down/Power-Up Timing (T_A = T_OPR)
Symbol
Parameter
Minimum Typical
tF
VCC slew from 4.5V to 0V
300
-
tR
VCC slew from 0V to 4.5V
100
-
tCSR
CS at VIH after power-up
20
-
t_DR
Data-retention and time-
keeping time
10
-
tWPT
Write-protect time for
external RAM
10
16
tCER
Chip enable recovery time tCSR
-
t_CED
Chip enable propagation
delay to external SRAM
-
7
Maximum
-
-
200
-
30
tCSR
10
Unit
Conditions
µs
µs
Internal write-protection
ms period after VCC passes VPFD
on power-up.
years ^{TA = 25°C, no load on VOUT or}
CEOUT.
Delay after VCC slows down
µs past VPFD before SRAM is
write-protected.
Time during which external
ms SRAM is write-protected after
VCC passes VPFD on power-up.
ns
Note:
Clock accuracy is better than ± 1 minute per month at 25°C for the period of tDR.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
Nov. 1993 C
3