ADS7866 Datasheet, PDF (3/24 Pages) Texas Instruments – 1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE

www.ti.com
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7866
At –40°C to 85°C, f_SAMPLE = 200 KSPS and f_SCLK = 3.4 MHz if 1.6 V ≤ V_DD ≤ 3.6 V; f_SAMPLE = 100 KSPS and f_SCLK = 1.7 MHz if
1.2 V ≤ V_DD < 1.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SYSTEM PERFORMANCE
Resolution
12
Bits
No missing codes
12
Bits
Integral linearity
–1.5
1.5 LSB⁽¹⁾
Differential linearity
–1
1.5 LSB
Offset error⁽²⁾
1.2 V ≤ V_DD < 1.6 V
1.6 V ≤ V_DD ≤ 3.6 V
Gain error⁽³⁾
1.2 V ≤ V_DD < 1.6 V
1.6 V ≤ V_DD ≤ 3.6 V
Total unadjusted error⁽⁴⁾
1.2 V ≤ V_DD < 1.6 V
1.6 V ≤ V_DD ≤ 3.6 V
SAMPLING DYNAMICS (See Timing Characteristics Section)
–2
2
LSB
–3
3
–2
2
LSB
–2
2
–2.5
2.5
LSB
–3.5
3.5
t_CONVERT
t_SAMPLE
f_SAMPLE
Conversion time
Acquisition time
Throughput rate
Aperture delay
f_SCLK = 3.4 MHz, 13 SCLK cycles
f_SCLK = 3.4 MHz, 1.6 V ≤ V_DD ≤ 3.6 V
f_SCLK = 3.4 MHz, 1.6 V ≤ V_DD ≤ 3.6 V
3.82
µs
0.64
µs
200 KSPS
10
ns
Aperture jitter
40
ps
DYNAMIC CHARACTERISTICS
SINAD
Signal-to-noise
and distortion
SNR
Signal-to-noise ratio
THD
Total harmonic distortion⁽⁵⁾
SFDR
Spurious free dynamic
range
Full-power bandwidth⁽⁶⁾
ANALOG INPUT
f_IN = 30 kHz, 1.2 V ≤ V_DD < 1.6 V
f_IN = 30 kHz, 1.6 V ≤ V_DD ≤ 3.6 V
f_IN = 30 kHz, 1.2 V ≤ V_DD < 1.6 V
f_IN = 30 kHz, 1.6 V ≤ V_DD ≤ 3.6 V
f_IN = 30 kHz, 1.2 V ≤ V_DD < 1.6 V
f_IN = 30 kHz, 1.6 V ≤ V_DD ≤ 3.6 V
f_IN = 30 kHz, 1.2 V ≤ V_DD < 1.6 V
f_IN = 30 kHz, 1.6 V ≤ V_DD ≤ 3.6 V
At 0.1 dB, 1.2 V ≤ V_DD < 1.6 V
At 0.1 dB, 1.6 V ≤ V_DD ≤ 3.6 V
At 3 dB, 1.2 V ≤ V_DD < 1.6 V
At 3 dB, 1.6 V ≤ V_DD ≤ 3.6 V
68
69
70
70
70
71
–70
–83
75
85
2
4
3
8
dB
dB
dB
dB
MHz
Full-scale input span⁽⁷⁾
VIN – GND
C_S
Input capacitance
Input leakage current
0
V_DD
V
12
pF
–1
1 µA
DIGITAL INPUT
Logic family , CMOS
V_IH
Input logic high level
1.2 V ≤ V_DD < 1.6 V
1.6 V ≤ V_DD < 1.8 V
1.8 V ≤ V_DD < 2.5 V
2.5 V ≤ V_DD ≤ 3.6 V
0.7×V_DD
0.7×V_DD
0.7×V_DD
2
3.6
3.6
V
3.6
3.6
(1) LSB = Least Significant BIt
(2) The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.
(3) The difference in the last code transition 011...111 to 111...111 from the ideal value of V_DD - 1 LSB with the offset error removed.
(4) The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of
offset error and gain error are included.
(5) The 2nd through 10th harmonics are used to determine THD.
(6) Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.
(7) Ideal input span which does not include gain or offset errors.
3