5962-9152101MXA Datasheet, PDF (3/16 Pages) Analog Devices – LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System

AD7874
TIMING CHARACTERISTICS1 (VDD = +5 V ؎ 5%, VSS = –5 V ؎ 5%, AGND = DGND = O V, tCLK = 2.5 MHz external unless
otherwise noted.)
Parameter
A, B Versions
S Version
Units
Conditions/Comments
t₁
t₂
t₃
t₄
t₅
t₆₂
t₇₃
t₈
t_CONV
t_CLK
50
0
60
0
60
57
5
45
130
31
32.5
31
35
10
50
ns min
CONVST Pulse Width
0
ns min
CS to RD Setup Time
70
ns min
RD Pulse Width
0
ns min
CS to RD Hold Time
60
ns max
RD to INT Delay
70
ns max
Data Access Time after RD
5
ns min
Bus Relinquish Time after RD
50
ns max
150
ns min
Delay Time between Reads
31
µs min
CONVST to INT, External Clock
32.5
µs max
CONVST to INT, External Clock
31
µs min
CONVST to INT, Internal Clock
35
µs max
CONVST to INT, Internal Clock
10
µs max
Minimum Input Clock Period
NOTES
1_{Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with}
tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2_{t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.}
3_{t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated}
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t ₇, quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T_A = +25°C unless otherwise noted)
V_DD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V_DD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V_SS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V_DD + 0.3 V
V_IN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to V_DD
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V_DD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to V_DD + 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . 1,000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1.6mA
TO OUTPUT
PIN
50pF
+2.1V
200µA
Figure 1. Load Circuit for Access Time
1.6mA
TO OUTPUT
PIN _50pF
+2.1V
200µA
Figure 2. Load Circuit for Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7874 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–