XIO2001_10 Datasheet, PDF (29/128 Pages) Texas Instruments – PCI Express™ to PCI Bus Translation Bridge

XIO2001
www.ti.com
SCPS212D – MAY 2009 – REVISED JANUARY 2010
A PCI Express MSI is generated based on the settings in the serial IRQ edge control register. If the
system is configured for edge mode, then an MSI message is sent when the corresponding serial IRQ
interface sample phase transitions from low to high. If the system is configured for level mode, then an
MSI message is sent when the corresponding IRQ status bit in the serial IRQ status register changes from
low to high.
The bridge has a dedicated SERIRQ terminal for all PCI bus devices that support serialized interrupts.
This SERIRQ interface is synchronous to the PCI bus clock input (CLK) frequency. The bridge always
generates a 17-phase serial IRQ stream. Internally, the bridge detects only 16 IRQ interrupts, IRQ0 frame
through IRQ15 frame. The IOCHCK frame is not monitored by the serial IRQ state machine and never
generates an IRQ interrupt or MSI message.
The multiple message enable (MM_EN) field determines the number of unique MSI messages that are
sent upstream on the PCI Express link. From 1 message to 16 messages, in powers of 2, are selectable.
If fewer than 16 messages are selected, then the mapping from IRQ interrupts to MSI messages is
aliased. Table 3-4 illustrates the IRQ interrupt to MSI message mapping based on the number of enabling
messages.
Table 3-4. IRQ Interrupt to MSI Message Mapping
IRQ
INTERRUPT
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
1 MESSAGE
ENABLED
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
2 MESSAGES
ENABLED
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
MSI MSG #0
MSI MSG #1
4 MESSAGES
ENABLED
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
8 MESSAGES ENABLED
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #4
MSI MSG #5
MSI MSG #6
MSI MSG #7
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #4
MSI MSG #5
MSI MSG #6
MSI MSG #7
16 MESSAGES
ENABLED
MSI MSG #0
MSI MSG #1
MSI MSG #2
MSI MSG #3
MSI MSG #4
MSI MSG #5
MSI MSG #6
MSI MSG #7
MSI MSG #8
MSI MSG #9
MSI MSG #10
MSI MSG #11
MSI MSG #12
MSI MSG #13
MSI MSG #14
MSI MSG #15
The MSI message format is compatible with the PCI Express request header format for 32-bit and 64-bit
memory write transactions. The system message and message number fields are included in bytes 0 and
1 of the data payload.
3.4.6 PCI Bus Clocks
The bridge has seven PCI bus clock outputs and one PCI bus clock input. Up to six PCI bus devices are
supported by the bridge.
Terminal PCLK66_SEL selects the default operating frequency. This signal works in conjunction with
terminal M66EN to determine the final output frequency. When PCLK66_SEL is asserted high then the
clock frequency will be either 66-MHz or 33-MHz depending on the state of M66EN. When M66EN is
asserted high then the clock frequency will be 66-MHz, when M66EN is de-asserted the clock frequency
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): XIO2001
Feature/Protocol Descriptions
29