UCC28251_15 Datasheet, PDF (29/55 Pages) Texas Instruments – UCC28251 Advanced PWM Controller With Prebias Operation

www.ti.com
9 Application and Implementation
UCC28251
SLUSBD8E – FEBRUARY 2013 – REVISED DECEMBER 2014
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The UCC28251 is a high performance PWM controller with advanced synchronous rectifier outputs and is ideally
suited for regulated half-bridge, full-bridge and push-pull converters. A dedicated internal pre-biased start up
control loop working in conjunction with a primary-side voltage loop achieves monotonic pre-biased start up for
either primary-side or secondary-side control applications. The UCC28251 architecture allows either voltage
mode or current mode control.
Input voltage feedforward can be implemented, allowing PWM ramp generator to improve the converter line
transient response. Advanced cycle-by-cycle current limit achieves volt-second balancing even during fault
conditions. The hiccup timer helps the system to stay within a safe operation range under over load conditions.
With a multifunction OVP/OTP pin, combinations of input voltage protection, output voltage protection and over
temperature protection can be implemented. The UCC28251 allows individual programming of dead time
between primary-side switch and secondary-side SRs, in order to allow optimal power stage design. Dead time
can also be reduced to zero, and this allows optimal system configuration considering the delays on the gate
driver stage. The UCC28251 also provides complete system level protection functions, including UVLO, thermal
shut down and over voltage, over current protection.
9.1.1 Error Amplifier and PWM Generation
The UCC28251 includes a high performance internal error amplifier with low input offset, high source/sink current
capability and high gain bandwidth (typical 3.5 MHz). The reference of the error amplifier (REF/EA+ pin) is set
externally to support flexible trimming of the voltage loop, and to make the controller flexible for both primary
side, as well as secondary-side control. The extra positive input for the error amplifier is the SS pin which is used
to externally program the soft-start time of the converter’s output.
During steady state operation, the primary switch duty cycle, D, is generated based on the external ramp on
RAMP/CS pin and the COMP pin voltage. A higher COMP pin voltage results in a larger duty cycle. The
secondary-side SR duty cycle is SR_D = (1-D), complementary to the primary-side duty cycle, without
considering the dead time between primary-side switch and secondary-side SR. The primary outputs begin to
switch when COMP pin voltage is above the 420 mV internal offset. The synchronous rectifier outputs, SRA and
SRB, follow after the primary outputs and have a minimum 50% duty cycle during startup. SRA and SRB
continue to be active and will only be disabled when UCC28251 is disabled (either through UVLO, EN shut
down, OVP and etc). According to the internal logic, the minimum pulse width for the primary-side OUTA and
OUTB is typically 100 ns.
During soft start, the primary-side switch duty cycle is generated based on the external ramp on RAMP/CS pin
and the COMP pin voltage. However, the duty cycle of secondary-side SR is generated based on an internal
ramp and the COMP pin voltage. When the converter is controlled on the primary side, an internal ramp is a
fixed ramp with 3-V peak voltage. When the converter is controlled on secondary side, an internal ramp is
generated based on the internal pre-biased start-up loop. An internal pre-biased start-up loop modifies the SR
duty cycle during soft start to achieve the optimal pre-biased start-up performance.
After the SS pin reaches 2.9 V, the pre-biased start-up control loop is disabled. The secondary-side SR
instantaneously changes into its steady state value as complementary to the primary-side duty cycle.
9.1.2 Prebiased Start Up
With the internal error amplifier, UCC28251 supports both primary-side control and secondary-side control. For
different control methods, the controller is configured accordingly and so is the pre-biased start-up control. During
soft start, both the primary-side switches’ duty cycle and secondary-side SRs’ duty cycle are increased. This
gradually increases the output voltage until steady state operation is reached, thereby reducing surge current.
Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: UCC28251
Submit Documentation Feedback
29