TPS658620 Datasheet, PDF (29/104 Pages) Texas Instruments – Advanced Power Management Unit

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TPS658620
Advanced Power Management Unit
SLVS993 – OCTOBER 2009
3.7 I²C COMMUNICATION PROTOCOL
The following conventions will be used when describing the communication protocol:
CONDITION
START sent from host
STOP sent from host
TPS658620 I²C slave address sent from host (WRITE)
TPS658620 register address sent from TPS658620 (READ)
Non-valid I²C slave address sent from host
Valid TPS658620 register address sent from host
Non-valid TPS658620 register address sent from host
I/O data byte (8 bits) sent from host to TPS658620
I/O data byte (8 bits) sent from TPS658620 to host
Acknowledge (ACK) from host
Not acknowledge (NACK) from host
Acknowledge (ACK) from TPS658620
Not acknowledge (NACK) from TPS658620
CODE
S
P
hA0
hA1
hA_N
HCMD
HCMD_N
hDATA
bqDATA
hA
hN
bqA
bqN
Figure 3-1. I²C Conditions
For normal data transfers, the data line (SDAT or PSDAT) is allowed to change only when the clock line
(SCLK or PSCLK) is low, and one clock pulse is used per bit of data. The data line must remain stable
whenever the clock line is high, as data changes when the clock is high are reserved for indicating the
start and stop conditions. Each data transfer is initiated with a start condition and terminated with a stop
condition.
When addressed, the TPS658620 device generates an acknowledge bit after the reception of each byte
by pulling the data line Low. The master device (microprocessor) must generate an extra clock pulse that
is associated with the acknowledge bit. After the acknowledge/not acknowledge bit, the TPS658620
leaves the data line high, enabling a STOP condition generation.
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